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Intel® 82870DH DDR Memory Hub (DMH)
Datasheet
Product Features
s Two independent DDR DIMM channels
per DMH.
— 4 DIMMs per DDR Channel.
— Registered PC1600 DDR DIMMs.
s Write Buffers to minimize large turnaround
times.
s Pass through architecture for Read and
Write accesses.
s Supports 128 Mb, 256 Mb, 512 Mb and
1 Gb DDR SDRAM technologies.
s Each DMH supports a wide range of
memory size.
— Up to 4 GB using 128 Mb device.
— Up to 8 GB using 256 Mb device.
— Up to 16 GB using 512 Mb device.
— Up to 32 GB using 1 Gb device.
s Support of RDRAM CMOS signals to
facilitate initialization and read/write of
registers.
s DMH internal registers accessed through
CMOS signal interface.
s Tunnels DDR SDRAM protocol over RSL.
s Integrated System Management Bus (SMB)
controller to read and write data from/to
SPD EEPROM on the DIMMs.
s 1.6 GB/s data rates in either 16-byte or
32-byte DDR DIMM transfer mode.
s 567 pin OLGA package.
Document Number: 251113-001
August 2002

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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked reservedor undefined.Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 82870DH DDR Memory Hub may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling1-800-548-
4725, or by visiting Intel's website at http://www.intel.com.
Intel and Itanium are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
Copyright © 2002, Intel Corporation. All rights reserved.
*Other names and brands may be claimed as the property of others.
I2C is a two-wire communication bus /protocol developed by Phillips. SMBus is a subset of the I2C bus/protocol developed by Intel. Implementation of
the I2C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including Phillips Electronics, N.V. and North American
Phillips Corporation.
ii Intel® E8870DH DDR Memory Hub (DMH) Datasheet

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Contents
1 Overview .........................................................................................................................1-1
1.1 System Architecture ...........................................................................................1-1
1.2 Supported Memory Configurations.....................................................................1-2
1.2.1 Memory Capacity ..................................................................................1-2
1.3 Terminology........................................................................................................1-3
1.4 Reference Documents........................................................................................1-4
1.5 Revision History .................................................................................................1-4
2 Signal Description ...........................................................................................................2-1
2.1 Main Channel Interface ......................................................................................2-1
2.2 Branch Channel Interface...................................................................................2-2
2.3 Reset and Test Signals ......................................................................................2-3
2.4 Voltage References............................................................................................2-4
3 Registers .........................................................................................................................3-1
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
3.14
3.15
3.16
3.17
Gen General Purpose Register .......................................................................3-1
DSTIM DIMM Strobe Timing Register.............................................................3-1
MCTIM Main Channel Timing Register ...........................................................3-3
BCTIM Branch Channel Timing Register ........................................................3-4
DGR DIMM Geometry Register.......................................................................3-5
MRF Mode Register Set Function Register.....................................................3-5
SDI SDRAM Initialization Register ..................................................................3-6
RCC RAMBUS Current Control Register ........................................................3-7
RIR RAC Initialization Register .......................................................................3-7
SPD Serial Presence Detect Status Register..................................................3-8
PWR Power Up Control Register ...................................................................3-9
VID Vendor Identification Register ................................................................3-10
RID Revision Identification Register..............................................................3-10
MUARS DMH Unified Access Register Select ..............................................3-10
MUARD DMH Unified Access Register Data ................................................3-11
3.15.1 DMH Unified Access Registers ...........................................................3-11
SPDID SPD Device ID Register ....................................................................3-13
DID Device Identification Register.................................................................3-13
4 Functional Description.....................................................................................................4-1
4.1 Operation Overview............................................................................................4-1
4.2 Main Channel to Branch Channel Translation....................................................4-2
4.2.1 MCP Format and Timing .......................................................................4-3
4.2.2 MCP Command Type Field ...................................................................4-3
4.2.3 MCP for DIMM Activate Command .......................................................4-3
4.2.4 MCP for DIMM Read/Write Command ..................................................4-4
4.2.5 MCP for Extended Commands..............................................................4-4
4.3 DMH Time Synchronization Packet....................................................................4-4
4.4 Main Channel Periodic Calibration .....................................................................4-5
4.4.1 Current Calibration ................................................................................4-5
4.4.2 Temperature Calibration........................................................................4-5
Intel® E8870DH DDR Memory Hub (DMH) Datasheet
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4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
4.13
4.14
Branch Channel Periodic Calibration .................................................................4-6
4.5.1 Slew Rate Calibration............................................................................4-6
4.5.2 Read Strobe 2.2 ns Delay Calibration ...................................................4-6
Transfer Mode....................................................................................................4-6
4.6.1 32-Byte Mode........................................................................................4-6
4.6.2 16-Byte Mode........................................................................................4-7
Write Buffers ...................................................................................................... 4-7
Memory Translation Rules .................................................................................4-7
4.8.1 Read Rules ...........................................................................................4-7
4.8.2 Write Rules............................................................................................ 4-8
4.8.3 Miscellaneous Rules .............................................................................4-8
4.8.4 Read-Hit Handling .................................................................................4-8
4.8.5 Burst Operation .....................................................................................4-8
4.8.6 Invalid and Unsupported DIMM Transactions .......................................4-9
Error Mechanisms ..............................................................................................4-9
4.9.1 Support for Memory Device Failure.......................................................4-9
System Clocking ................................................................................................4-9
Serial Interface .................................................................................................4-10
4.11.1 Overview .............................................................................................4-10
4.11.2 MSIO Transaction Packet Formats .....................................................4-10
4.11.3 MSIO Bus Interface .............................................................................4-11
4.11.4 BSIO Bus Interface .............................................................................4-12
DDR SDRAM Transactions ..............................................................................4-15
4.12.1 DIMM Initialization ...............................................................................4-15
Reset ................................................................................................................ 4-16
4.13.1 Power Good Sequence .......................................................................4-16
4.13.2 Hard Reset ..........................................................................................4-17
4.13.3 Local Reset .........................................................................................4-17
4.13.4 MSIO Local Reset ...............................................................................4-17
Initialization ......................................................................................................4-18
4.14.1 RAC Initialization .................................................................................4-18
4.14.2 DDR DIMM Sizing ...............................................................................4-18
4.14.3 DDR DIMM Initialization ......................................................................4-18
4.14.4 DDR Read Strobe Delay Calibration ...................................................4-19
4.14.5 DDR DIMM Path Delay Calibration .....................................................4-19
5 Electrical Specifications ..................................................................................................5-1
5.1 Non-Operational Maximum Rating .....................................................................5-1
5.2 Operation Power Delivery Specification.............................................................5-1
5.3 Main Channel Interface ......................................................................................5-2
5.3.1 Main Channel Interface Reference Voltage Specification .....................5-2
5.3.2 DC Specifications.................................................................................. 5-2
5.3.3 AC Specifications .................................................................................. 5-3
5.4 DDR Interface ....................................................................................................5-3
5.4.1 Signal Group .........................................................................................5-3
5.4.2 DDR Reference Voltage Requirements ................................................5-4
5.4.3 DC Specifications.................................................................................. 5-4
5.4.4 AC Specifications .................................................................................. 5-4
5.5 Miscellaneous Signals Interface.........................................................................5-6
5.5.1 Signal Groups .......................................................................................5-6
5.5.2 DC Characteristics ................................................................................5-6
5.5.3 AC Specification ....................................................................................5-7
iv Intel® E8870DH DDR Memory Hub (DMH) Datasheet

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6 Ballout and Package Information ....................................................................................6-1
6.1 567-Ball OLGA1 Package Information ...............................................................6-1
6.2 Ballout Signal List...............................................................................................6-4
7 Testability ........................................................................................................................7-1
7.1 Parametric Test Mode ........................................................................................7-1
Figures
1-1
1-2
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
5-1
5-2
6-1
6-2
6-3
Fully Loaded SNC Example ...............................................................................1-1
DMH Driving Both DIMM Channels, Four DIMMs per Channel .........................1-2
DMH Block Diagram...........................................................................................4-2
Driving MCP to DIMM Address and Control Lines .............................................4-3
Phase Shifted MCP Command State Tracker and Correction ...........................4-4
Example of Valid Write Command Ordering ......................................................4-8
DRCG Connection Diagram .............................................................................4-10
Register Read MSIO Transaction ....................................................................4-10
Register Write MSIO Transaction.....................................................................4-11
MSIO Register Read Transaction ....................................................................4-12
MSIO Register Write Transaction.....................................................................4-12
Connection of DIMM Serial I/O Signals............................................................4-13
Random Byte Read Timing ..............................................................................4-14
Byte Write Register Timing...............................................................................4-15
PWRGOOD Sequence Method 1.....................................................................4-16
PWRGOOD Sequence Method 2.....................................................................4-17
SIO Reset Sequence........................................................................................4-17
SSTL-2 Common Clock AC Timing....................................................................5-5
SSTL-2 Source Synchronous AC Timing ...........................................................5-6
567-Ball (DMH) OLGA1 Package Dimensions Top View................................6-1
567-Ball (DMH) OLGA1 Package Dimensions Bottom View...........................6-2
567-Ball (DMH) OLGA1 Solder Balls Detail .......................................................6-3
Tables
1-1
2-1
2-2
2-3
2-4
3-1
4-1
4-2
4-3
4-4
4-5
5-1
5-2
5-3
5-4
5-5
5-7
5-6
5-8
Memory Size ......................................................................................................1-3
Main Channel Interface Signals .........................................................................2-1
Branch Channel Interface Signals......................................................................2-2
Reset and Miscellaneous Signals ......................................................................2-3
Voltage Reference Signals.................................................................................2-4
Unified Access Register Definitions .................................................................3-11
Encoding of ST and SF ......................................................................................4-3
Write Buffer Burst Operation for Read-Hit Operations .......................................4-9
MSIO Packet Field Definitions..........................................................................4-11
SCK Clock Divider Frequency Table................................................................4-14
DDR SDRAM Command Encoding for SDI Register .......................................4-16
Absolute Maximum Non-Operational DC Ratings at the Package Pin...............5-1
Voltage and Current Specifications ....................................................................5-1
DMH Main Channel Signal Groups ....................................................................5-2
Main Channel Vref Specification ........................................................................5-2
RSL Data Group, DC Parameters ......................................................................5-2
Main Channel CMOS 1.8 I/ODC Parameters .................................................5-3
RSL Clocks, DC Parameters..............................................................................5-3
DMH DDR Signal Groups...................................................................................5-3
Intel® E8870DH DDR Memory Hub (DMH) Datasheet
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