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Intel® E8870SP Scalability Port Switch
(SPS) Datasheet
Product Features
s Scalability Port (SP):
— Six SPs with 3.2 GB/s peak bandwidth
per direction per SP.
— Bi-directional SPs for a total bandwidth
of 38.4 GB/s.
s Integrated Snoop Filter:
— 1 MB 12-way set associative tag array
capable of maintaining state of 200K
cache lines.
— Partitioned into four interleaves, each
interleave can be accessed in parallel.
— Supports up to 266M look-up and
update (LUU) operations per second.
— Pseudo Least Recently Used (PLRU)
replacement algorithm, with updates on
look-ups and invalidates.
— ECC coverage, with correction of
single bit errors, detection of double bit
errors.
— Fast array initialization and/or self test
through configuration register access.
s Multiple Processor Node Support:
— Conflict detection logic to maintain
memory consistency for coherent
memory across multiple processor
nodes.
— Advanced address mapping and decode
capabilities enable flexible routing of
transactions based on address and/or
transaction type.
s Internal Interconnect:
— A six-ported dual lane crossbar network
routes transaction packets from one SP
port to another.
— Separate bypass buses for low latency
snoop look-up and response connection
between ports and interleaves.
s System Management Bus (SMBus) 2.0
slave interface for server management with
packet error checking.
s Reliability, Availability, and Serviceability
(RAS):
— Sideband access to configuration
registers via SMBus or JTAG.
— End-to-end ECC for all interfaces.
— Fault detection and logging.
— Signal connectivity testing via
boundary scan.
s Packaging:
— 42.5 mm x 42.5 mm.
— 1012-pin organic LAN grid array
(OLGA) package-2B.
Document Number: 252034-001
November 2002

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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked reservedor undefined.Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Itanium 2 processor, E8870 chipset, and E8870SP scalability port switch (SPS) may contain design defects or errors known as errata which may
cause the product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling1-800-548-
4725, or by visiting Intel's website at http://www.intel.com.
Intel and Itanium are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
Copyright © 2002, Intel Corporation. All rights reserved.
*Other names and brands may be claimed as the property of others.
ii Intel® E8870SP Scalability Port Switch (SPS) Datasheet

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Contents
1 Introduction......................................................................................................................1-1
1.1 Overview ............................................................................................................1-1
1.2 Feature Summary...............................................................................................1-1
1.2.1 Interfaces...............................................................................................1-1
1.2.2 Multinode Routing, Cache Coherency, and Memory Consistency ........1-1
1.2.3 Reliability and Serviceability..................................................................1-1
1.3 SPS Blocks.........................................................................................................1-2
1.3.1 Interleaves.............................................................................................1-2
1.3.2 Ports ......................................................................................................1-3
1.3.3 Interconnect...........................................................................................1-3
1.4 Reference Documents........................................................................................1-3
1.5 Revision History .................................................................................................1-4
2 Signal Descriptions..........................................................................................................2-1
2.1 Conventions .......................................................................................................2-1
2.2 SPS Pin List .......................................................................................................2-2
3 Configuration Registers...................................................................................................3-1
3.1 Access Mechanism ............................................................................................3-1
3.1.1 Conflict Resolution ................................................................................3-1
3.2 Device Mapping..................................................................................................3-1
3.2.1 Assignment of Device Number..............................................................3-1
3.2.2 Device Mapping Table...........................................................................3-2
3.3 Register Attributes..............................................................................................3-2
3.3.1 SMBus-Initiated Register Access ..........................................................3-3
3.4 SPS Configuration Register Definitions..............................................................3-3
3.5 SPS PCI Standard Configuration Registers All Functions ..............................3-3
3.5.1 VID: Vendor Identification Register .......................................................3-3
3.5.2 DID: Device Identification Register........................................................3-3
3.5.3 RID: Revision ID Register .....................................................................3-4
3.5.4 CCR: Class Code Register....................................................................3-4
3.5.5 HDR: Header Type Register .................................................................3-5
3.5.6 SVID: Subsystem Vendor Identification Register ..................................3-5
3.5.7 SDID: Subsystem Device Identification Register ..................................3-5
3.6 SP Port Configuration Register Functions 0:5.................................................3-5
3.6.1 CBC: Chip Boot Configuration...............................................................3-5
3.6.2 SPINCO: SP Interface Control ..............................................................3-7
3.6.3 RECSPPD: Recoverable Error Control Information of SPPD ...............3-9
3.6.4 RECSPL: Recoverable Error Control Information of SPL .....................3-9
3.6.5 REDSPL: Recoverable Error Data Log SPL .........................................3-9
3.6.6 MIR[5:0]: Memory Interleave Range Registers ...................................3-10
3.6.7 SIOH_MAP: SIOH Mapping Register..................................................3-11
3.6.8 MMIOLS: Memory-Mapped I/O Low Segment Register......................3-11
3.6.9 MMIOHS: Memory-Mapped I/O High Segment Register ....................3-11
3.6.10 SARS: SAPIC Range Segment Register ............................................3-12
3.6.11 IOPORTS: I/O Space Segment Address.............................................3-12
3.6.12 PSEG: PCI Configuration Bus Segment Address ...............................3-12
3.6.13 CB_PORT: Compatibility Bus Port Number ........................................3-13
Intel® E8870SP Scalability Port Switch (SPS) Datasheet
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3.6.14 VGA_PORT: VGA Port Number..........................................................3-13
3.6.15 PMISC: Port Miscellaneous.................................................................3-13
3.7 SPS Global Registers Function 6 Only .........................................................3-14
3.7.1 FERRST[1:0]: First Error Status..........................................................3-14
3.7.2 SERRST[1:0]: Two or More Error Status ............................................3-16
3.7.3 ERRMASK[1:0]: ERRST MASK ..........................................................3-16
3.7.4 SPSGLB: SPS Global Register ...........................................................3-16
3.7.5 PERFCON: Performance Monitor Master Control...............................3-17
3.7.6 PMD[1:0]: Performance Monitor Data .................................................3-18
3.7.7 PCMP[1:0]: Performance Monitor Compare........................................3-18
3.7.8 PMR[1:0]: Performance Monitor Response.........................................3-18
3.8 Interleave Configuration Registers Functions 6 and 7 ..................................3-20
3.8.1 NRESPPC[1:0]: Non-recoverable Error Control Information
of SPPC ..............................................................................................3-21
3.8.2 RECSPPC[1:0]: Recoverable Error Control Information
of SPPC ..............................................................................................3-21
3.8.3 SYS_CFG[1:0]: System Configuration ................................................3-22
3.8.4 ERRCOM[1:0]: Error Command..........................................................3-22
3.8.5 NID_DEF[1:0]: Node ID Definition.......................................................3-23
3.8.6 REM_CDEF[1:0] Remote Component Definition ................................3-23
3.8.7 SFCMD: Snoop Filter Tag/LRU Array Command................................3-24
3.8.8 SFDATA: Snoop Filter Tag/LRU Array Data .......................................3-24
3.8.9 PME[1:0]: Performance Monitor Events ..............................................3-25
4 Address Mapping ............................................................................................................4-1
4.1 Memory Map ...................................................................................................... 4-1
4.1.1 SPS Memory Address Space Regions..................................................4-1
4.1.2 Memory-Mapped I/O Regions ...............................................................4-2
4.1.3 Routing Interrupts.................................................................................. 4-3
4.2 Address Mapping in I/O Space ..........................................................................4-3
4.3 Address Mapping to Access Snoop Filter ..........................................................4-4
4.4 Illegal Addresses ................................................................................................4-4
5 Functional Description.....................................................................................................5-1
5.1 Interfaces ...........................................................................................................5-1
5.1.1 Scalability Port ......................................................................................5-1
5.1.2 JTAG .....................................................................................................5-1
5.1.3 SMBus Interface....................................................................................5-1
5.1.4 GPIO .....................................................................................................5-1
5.2 Snoop Filter........................................................................................................5-2
5.2.1 Coverage and Addressing.....................................................................5-2
5.2.2 Replacement Algorithm .........................................................................5-3
5.2.3 Snoop Filter Operations and Interfaces ................................................5-3
5.2.4 Error Correction and Logging ................................................................5-4
5.2.5 Snoop Filter Performance .....................................................................5-4
5.3 Interconnect .......................................................................................................5-4
5.3.1 Bypass Buses .......................................................................................5-4
5.3.2 Crossbar Switch ....................................................................................5-5
6 Clocking .......................................................................................................................... 6-1
6.1 SPS Reference Clock (SYSCLK).......................................................................6-1
6.2 Other Functional and Electrical Requirements...................................................6-1
iv Intel® E8870SP Scalability Port Switch (SPS) Datasheet

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6.2.1
6.2.2
6.2.3
6.2.4
Spread Spectrum Support.....................................................................6-1
No Stop Clock or Thermal Shutdown ....................................................6-1
SMBus Clocking ....................................................................................6-1
JTAG Test Access Port .........................................................................6-1
7 Reliability, Availability and Serviceability.........................................................................7-1
7.1 Data Integrity ......................................................................................................7-1
7.1.1 End-to-End Error Detection ...................................................................7-1
7.1.2 Error Reporting......................................................................................7-2
7.1.3 Interface Details ....................................................................................7-3
7.1.4 Time-out ................................................................................................7-3
8 Electrical Specification ....................................................................................................8-1
8.1 Non-operational Maximum Rating......................................................................8-1
8.2 Operational Power Delivery Specification ..........................................................8-1
8.3 Scalability Port Signal Group..............................................................................8-2
8.4 SMBus and TAP Electrical Specifications ..........................................................8-2
8.5 DC Specifications ...............................................................................................8-3
8.6 AC Specifications ...............................................................................................8-4
8.6.1 AC Timing Waveforms ..........................................................................8-5
8.7 Miscellaneous Signal Pins..................................................................................8-6
8.7.1 Signal Groups........................................................................................8-6
8.7.2 DC Characteristics ................................................................................8-7
8.8 AC Specification .................................................................................................8-8
8.9 Intel® E8870 Chipset Clock Signal Groups ........................................................8-9
9 Ballout and Package Information ....................................................................................9-1
9.1 1012-Ball OLGA2b Package Information ...........................................................9-1
10 Testability ......................................................................................................................10-1
10.1 Test Access Port ..............................................................................................10-1
10.1.1 The TAP Logic.....................................................................................10-1
10.1.2 Accessing the TAP Logic ....................................................................10-2
10.2 Public TAP Instructions ....................................................................................10-4
10.3 TAP Registers ..................................................................................................10-5
Figures
1-1
4-1
4-2
8-1
8-2
8-3
9-1
9-2
9-3
10-1
10-2
10-3
10-4
SPS Block Diagram............................................................................................1-2
System Memory Address Space ........................................................................4-1
Example of Mapping MMIO Regions..................................................................4-3
TAP DC Thresholds ...........................................................................................8-4
TAP and SMBus Valid Delay Timing Waveform ................................................8-5
TCK and SM_CLK Clock Waveform ..................................................................8-6
1012-Ball OLGA2b Package Dimensions Top View .......................................9-1
1012-Ball OLGA2b Package Dimensions Bottom View ..................................9-2
1012-Ball OLGA2b Solder Ball Detail.................................................................9-3
TAP Controller Signals .....................................................................................10-1
Simplified Block Diagram of TAP Controller.....................................................10-2
TAP Controller State Diagram..........................................................................10-3
TAP Instruction Register ..................................................................................10-6
Intel® E8870SP Scalability Port Switch (SPS) Datasheet
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