55N03LT.pdf 데이터시트 (총 11 페이지) - 파일 다운로드 55N03LT 데이타시트 다운로드

No Preview Available !

www.DataSheet4U.com
Philips Semiconductors
N-channel TrenchMOStransistor
Logic level FET
Product specification
PHP55N03LT, PHB55N03LT
PHD55N03LT
FEATURES
’Trench’ technology
• Very low on-state resistance
• Fast switching
• Low thermal resistance
• Logic level compatible
SYMBOL
d
g
s
QUICK REFERENCE DATA
VDSS = 25 V
ID = 55 A
RDS(ON) 14 m(VGS = 10 V)
RDS(ON) 18 m(VGS = 5 V)
GENERAL DESCRIPTION
N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using ’trench’ technology.
Applications:-
• High frequency computer motherboard d.c. to d.c. converters
• High current switching
The PHP55N03LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB55N03LT is supplied in the SOT404 (D2PAK) surface mounting package.
The PHD55N03LT is supplied in the SOT428 (DPAK)surface mounting package.
PINNING
SOT78 (TO220AB) SOT404 (D2PAK)
PIN DESCRIPTION
1 gate
tab
tab
SOT428 (DPAK)
tab
2 drain 1
3 source
tab drain
1 23
2
13
2
13
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
VDSS
VDGR
VGS
VGSM
ID
IDM
Ptot
Tj, Tstg
Drain-source voltage
Drain-gate voltage
Gate-source voltage (DC)
Gate-source voltage (pulse
peak value)
Drain current (DC)
Drain current (pulse peak
value)
Total power dissipation
Operating junction and
storage temperature
Tj = 25 ˚C to 175˚C
Tj = 25 ˚C to 175˚C; RGS = 20 k
Tj 150˚C
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
Tmb = 25 ˚C
MIN.
-
-
-
-
-
-
-
-
- 55
MAX.
25
25
± 15
± 20
55
38
220
103
175
UNIT
V
V
V
V
A
A
A
W
˚C
1 It is not possible to make connection to pin:2 of the SOT404 or SOT428 packages.
October 1999
1
Rev 1.200

No Preview Available !

www.DataSheet4U.com
Philips Semiconductors
N-channel TrenchMOStransistor
Logic level FET
Product specification
PHP55N03LT, PHB55N03LT
PHD55N03LT
THERMAL RESISTANCES
SYMBOL PARAMETER
Rth j-mb
Rth j-a
Thermal resistance junction
to mounting base
Thermal resistance junction
to ambient
CONDITIONS
SOT78 package, in free air
SOT404 and SOT428 packages, pcb
mounted, minimum footprint
MIN. TYP. MAX. UNIT
- - 1.45 K/W
- 60 - K/W
- 50 - K/W
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
WDSS
Drain-source non-repetitive ID = 25 A; VDD 15 V;
unclamped inductive turn-off VGS = 5 V; RGS = 50 ; Tmb = 25 ˚C
energy
MIN.
-
MAX.
60
UNIT
mJ
ELECTRICAL CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
V(BR)DSS
VGS(TO)
RDS(ON)
gfs
IGSS
IDSS
Qg(tot)
Qgs
Qgd
td on
tr
td off
tf
Ld
Ld
Ls
Drain-source breakdown
voltage
Gate threshold voltage
Drain-source on-state
resistance
Forward transconductance
Gate source leakage current
Zero gate voltage drain
current
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
VGS = 0 V; ID = 0.25 mA;
Tj = -55˚C
VDS = VGS; ID = 1 mA
Tj = 175˚C
Tj = -55˚C
VGS = 10 V; ID = 25 A
VGS = 10 V; ID = 25 A (SOT428 package)
VGS = 5 V; ID = 25 A
VGS = 5 V; ID = 25 A; Tj = 175˚C
VDS = 25 V; ID = 25 A
VGS = ±5 V; VDS = 0 V
VDS = 25 V; VGS = 0 V;
Tj = 175˚C
ID = 55 A; VDD = 15 V; VGS = 5 V
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 15 V; ID = 25 A;
VGS = 10 V; RG = 5
Resistive load
Internal drain inductance
Internal drain inductance
Internal source inductance
Measured tab to centre of die
Measured from drain lead to centre of die
(SOT78 package only)
Measured from source lead to source
bond pad
Ciss Input capacitance
Coss Output capacitance
Crss Feedback capacitance
VGS = 0 V; VDS = 20 V; f = 1 MHz
MIN. TYP. MAX. UNIT
25 -
-V
22 -
-V
1 1.5 2
V
0.5 -
-V
- - 2.3 V
- 11 14 m
- 14 16 m
- 15 18 m
- - 34 m
10 28 - S
- 10 100 nA
- 0.05 10 µA
- - 500 µA
- 20 - nC
- 8 - nC
- 9 - nC
- 7 15 ns
- 56 80 ns
- 57 80 ns
- 38 50 ns
- 3.5 - nH
- 4.5 - nH
- 7.5 - nH
- 1230 -
- 354 -
- 254 -
pF
pF
pF
October 1999
2
Rev 1.200

No Preview Available !

www.DataSheet4U.com
Philips Semiconductors
N-channel TrenchMOStransistor
Logic level FET
Product specification
PHP55N03LT, PHB55N03LT
PHD55N03LT
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
IS Continuous source current
(body diode)
ISM Pulsed source current (body
diode)
VSD Diode forward voltage
IF = 25 A; VGS = 0 V
IF = 55 A; VGS = 0 V
trr
Reverse recovery time
IF = 20 A; -dIF/dt = 100 A/µs;
Qrr Reverse recovery charge VGS = 0 V; VR = 25 V
MIN. TYP. MAX. UNIT
- - 55 A
- - 220 A
- 0.9 1.2 V
- 1.0 -
- 87 - ns
- 0.1 - µC
Normalised Power Derating, PD (%)
100
90
80
70
60
50
40
30
20
10
0
0 25 50 75 100 125 150
Mounting Base temperature, Tmb (C)
Fig.1. Normalised power dissipation.
PD% = 100PD/PD 25 ˚C = f(Tmb)
175
Normalised Current Derating, ID (%)
100
90
80
70
60
50
40
30
20
10
0
0 25 50 75 100 125
Mounting Base temperature, Tmb (C)
150
175
Fig.2. Normalised continuous drain current.
ID% = 100ID/ID 25 ˚C = f(Tmb); VGS 5 V
1000 Peak Pulsed Drain Current, IDM (A)
RDS(on) = VDS/ ID
100
10
D.C.
tp = 10 us
100 us
1 ms
10 ms
100 ms
1
1 10 100
Drain-Source Voltage, VDS (V)
Fig.3. Safe operating area
ID & IDM = f(VDS); IDM single pulse; parameter tp
Transient thermal impedance, Zth j-mb (K/W)
10
1 D = 0.5
0.2
0.1
0.1 0.05
0.02
P
D
D = tp/T
tp
single pulse
0.01
1E-06
1E-05
T
1E-04
1E-03
1E-02
Pulse width, tp (s)
1E-01
1E+00
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
October 1999
3
Rev 1.200

No Preview Available !

www.DataSheet4U.com
Philips Semiconductors
N-channel TrenchMOStransistor
Logic level FET
Product specification
PHP55N03LT, PHB55N03LT
PHD55N03LT
Drain Current, ID (A)
50
VGS = 10 V 5 V
45
4.5 V
Tj = 25 C
40
35
30 3 V
25
2.8 V
20
15 2.6 V
10
5
0
0
2.4 V
2.2 V
2V
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
Drain-Source Voltage, VDS (V)
2
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
Drain-Source On Resistance, RDS(on) (Ohms)
0.1
2.2 V 2.4 V 2.6 V
2.8V
0.09
Tj = 25 C
0.08
3V
0.07
0.06
0.05
0.04
0.03
0.02 5 V VGS =4.5 V
0.01
0
0
10V
5 10 15 20 25 30 35 40 45 50
Drain Current, ID (A)
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VGS
Drain current, ID (A)
40
VDS > ID X RDS(ON)
35
30
25
20
15
10
175 C
5 Tj = 25 C
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Gate-source voltage, VGS (V)
Fig.7. Typical transfer characteristics.
ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj
Transconductance, gfs (S)
30
VDS > ID X RDS(ON)
25
Tj = 25 C
20
175 C
15
10
5
0
0 5 10 15 20 25 30 35 40
Drain current, ID (A)
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID); conditions: VDS = 25 V
Normalised On-state Resistance
2
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
Junction temperature, Tj (C)
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj)
Threshold Voltage, VGS(TO) (V)
2.25
2
maximum
1.75
1.5
typical
1.25
1 minimum
0.75
0.5
0.25
0
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
Junction Temperature, Tj (C)
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
October 1999
4
Rev 1.200

No Preview Available !

www.DataSheet4U.com
Philips Semiconductors
N-channel TrenchMOStransistor
Logic level FET
Product specification
PHP55N03LT, PHB55N03LT
PHD55N03LT
Drain current, ID (A)
1.0E-01
VDS = 5 V
1.0E-02
1.0E-03
1.0E-04
minimum
typical
maximum
1.0E-05
1.0E-06
0 0.5 1 1.5 2 2.5 3
Gate-source voltage, VGS (V)
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
Capacitances, Ciss, Coss, Crss (pF)
10000
1000
Ciss
Coss
Crss
100
0.1
1 10
Drain-Source Voltage, VDS (V)
100
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
Gate-source voltage, VGS (V)
15
14 ID = 55A
13 Tj = 25 C
12
11 VDD = 15 V
10
9
8
7
6
5
4
3
2
1
0
0 5 10 15 20 25 30 35 40 45 50
Gate charge, QG (nC)
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); parameter VDS
Source-Drain Diode Current, IF (A)
50
VGS = 0 V
45
40
35
30 175 C
25
Tj = 25 C
20
15
10
5
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5
Source-Drain Voltage, VSDS (V)
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
October 1999
5
Rev 1.200