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DP80390
Pipelined High Performance
8-bit Microcontroller
ver 4.02
OVERVIEW
DP80390 is an ultra high performance,
speed optimized soft core of a single-chip 8-
bit embedded controller dedicated for opera-
tion with fast (typically on-chip) and slow (off-
chip) memories. It supports up to 8 MB of lin-
ear code and 16 MB of linear data spaces. The
core has been designed with a special concern
about performance to power consumption
ratio. This ratio is extended by an advanced
power management unit PMU.
DP80390 soft core is 100% binary-
compatible with the industry standard 80390 &
8051 8-bit microcontrollers. There are two con-
figurations of DP80390: Harward where inter-
nal data and program buses are separated,
and von Neumann with common program and
external data bus. DP80390 has Pipelined
RISC architecture 10 times faster compared
to standard architecture and executes 85-200
million instructions per second. This per-
formance can also be exploited to great advan-
tage in low power applications where the core
can be clocked over ten times more slowly
than the original implementation for no per-
formance penalty.
DP80390 is delivered with fully auto-
mated testbench and complete set of tests
allowing easy package validation at each stage
of SoC design flow.
CPU FEATURES
100% software compatible with industry
standard 80390 & 8051
LARGE mode – 8051 instruction set
FLAT mode – 80390 instruction set
Pipelined RISC architecture enables to
execute instructions 10 times faster com-
pared to standard 8051
24 times faster multiplication
12 times faster addition
Up to 256 bytes of internal (on-chip) Data
Memory
Up to 8M bytes of linear Program Memory
64 kB of internal (on-chip) Program Memory
8 MB external (off-chip) Program Memory
Up to 16M bytes of external (off-chip) Data
Memory
User programmable Program Memory Wait
States solution for wide range of memories
speed
User programmable External Data Memory
Wait States solution for wide range of
memories speed
De-multiplexed Address/Data bus to allow
easy connection to memory
Dedicated signal for Program Memory
writes.
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

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Interface for additional Special Function
Registers
Fully synthesizable, static synchronous
design with positive edge clocking and no
internal tri-states
Scan test ready
2.0 GHz virtual clock frequency in a 0.25u
technological process
PERIPHERALS
DoCD™ debug unit
Processor execution control
Run
Halt
Step into instruction
Skip instruction
Read-write all processor contents
Program Counter (PC)
Program Memory
Internal (direct) Data Memory
Special Function Registers (SFRs)
External Data Memory
Code execution breakpoints
one real-time PC breakpoint
unlimited number of real-time OPCODE break-
points
Hardware execution watch-point
one at Internal (direct) Data Memory
one at Special Function Registers (SFRs)
one at External Data Memory
Hardware watch-points activated at a certain
address by any write into memory
address by any read from memory
address by write into memory a required data
address by read from memory a required data
Unlimited number of software watch-points
Internal (direct) Data Memory
Special Function Registers (SFRs)
External Data Memory
Unlimited number of software breakpoints
Program Memory(PC)
Automatic adjustment of debug data transfer
speed rate between HAD and Silicon
JTAG Communication interface
Power Management Unit
Power management mode
Switchback feature
Stop mode
Interrupt Controller
2 priority levels
2 external interrupt sources
3 interrupt sources from peripherals
Four 8-bit I/O Ports
Bit addressable data direction for each line
Read/write of single line and 8-bit group
Two 16-bit timer/counters
Timers clocked by internal source
Auto reload 8-bit timers
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are trademarks of their respective owners.
Externally gated event counters
Full-duplex serial port
Synchronous mode, fixed baud rate
8-bit asynchronous mode, fixed baud rate
9-bit asynchronous mode, fixed baud rate
9-bit asynchronous mode, variable baud rate
CONFIGURATION
The following parameters of the DP80390 core
can be easy adjusted to requirements of dedi-
cated application and technology. Configura-
tion of the core can be prepared by effortless
changing appropriate constants in package file.
There is no need to change any parts of the
code.
Internal
type
Program
Memory
- synchronous
- asynchronous
Internal Program
Memory size
ROM
-
-
0 - 64kB
Internal Program
Memory size
RAM
-
-
0 - 64kB
Internal Program
fixed size
Memory
- true
- false
Interrupts
-
subroutines
location
Power Management Mode
- used
- unused
Stop mode
- used
- unused
DoCDdebug unit
- used
- unused
Besides mentioned above parameters all
available peripherals and external interrupts
can be excluded from the core by changing
appropriate constants in package file.
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DELIVERABLES
Source code:
VHDL Source Code or/and
VERILOG Source Code or/and
Encrypted, or plain text EDIF netlist
VHDL & VERILOG test bench environment
Active-HDL automatic simulation macros
ModelSim automatic simulation macros
Tests with reference responses
Technical documentation
Installation notes
HDL core specification
Datasheet
Synthesis scripts
Example application
Technical support
IP Core implementation support
3 months maintenance
Delivery the IP Core updates, minor and
major versions changes
Delivery the documentation updates
Phone & email support
LICENSING
Comprehensible and clearly defined licensing
methods without royalty fees make using of IP
Core easy and simply.
Single Design license allows using IP Core in
single FPGA bitstream and ASIC implementa-
tion. It also permits FPGA prototyping before
ASIC production.
Unlimited Designs license allows using IP Core
in unlimited number of FPGA bitstreams and
ASIC implementations.
In all cases number of IP Core instantiations
within a design, and number of manufactured
chips are unlimited. There is no time of use
limitations.
Single Design license for
VHDL, Verilog source code called HDL Sour-
ce
Encrypted, or plain text EDIF called Netlist
Unlimited Designs license for
HDL Source
Netlist
Upgrade from
Netlist to HDL Source
Single Design to Unlimited Designs
DESIGN FEATURES
PROGRAM MEMORY:
The DP80390 soft core is dedicated for
operation with Internal and External Pro-
gram Memory. It maximal linear size is
equal to 8 MB. Internal Program Memory
can be implemented as:
ROM located in address range between
0000h ÷ (ROMsize-1)
RAM located in address range between
(64kB-RAMsize) ÷ FFFFh
External Program Memory can be im-
plemented as ROM or RAM located in ad-
dress range between ROMsize ÷ 8 MB ex-
cluding area occupied by RAMsize.
INTERNAL DATA MEMORY:
The DP80390 can address Internal Data
Memory of up to 256 bytes The Internal
Data Memory can be implemented as Sin-
gle-Port synchronous RAM.
EXTERNAL DATA MEMORY:
The DP80390 soft core can address up
to 16 MB of External Data Memory. Extra
DPX (Data Pointer eXtended) register is
used for segments swapping.
USER SPECIAL FUNCTION REGISTERS:
Up to 104 External (user) Special Func-
tion Registers (ESFRs) may be added to
the DP80390 design. ESFRs are memory
mapped into Direct Memory between ad-
dresses 0x80 and 0xFF in the same man-
ner as core SFRs and may occupy any ad-
dress that is not occupied by a core SFR.
WAIT STATES SUPPORT:
The DP80390 soft core is dedicated for
operation with wide range of Program and
Data memories. Slow Program and Exter-
nal Data memory may assert a memory
Wait signal to hold up CPU activity.
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

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SYMBOL
BLOCK DIAGRAM
port0i(7:0)
port1i(7:0)
port2i(7:0)
port3i(7:0)
prgromdata(7:0)
prgramdata(7:0)
xdatai(7:0)
ready
iprgromsize(2:0)
iprgramsize(2:0)
sxdmxdatai(7:0)
ramdatai(7:0)
sfrdatai(7:0)
int0
int1
t0
t1
gate0
gate1
rxdi
tdi
tck
tms
reset
clk
port0o(7:0)
port1o(7:0)
port2o(7:0)
port3o(7:0)
prgaddr(15:0)
prgdatao(7:0)
prgramwr
xaddr(23:0)
xdatao(7:0)
xdataz
xprgrd
xprgwr
xdatard
xdatawr
sxdmadd(15:0)
sxdmdatao(7:0)
sxdmwe
sxdmoe
ramaddr(7:0)
ramdtao(7:0)
ramwe
ramoe
sfraddr(6:0)
sfrdatao(7:0)
sfroe
sfrwe
stop
pmm
rxdo
txd
tdo
rtck
coderun
debugacs
rsto
prgramdata(7:0)
prgromdata(7:0)
prgaddr(15:0)
prgdatao(7:0)
prgramwr
xaddr(23:0)
xdatao(7:0)
xdatai(7:0)
xdataz
ready
xprgrd
xprgwr
xdatard
xdatawr
iprgromsize(2:0)
iprgramsize(2:0)
ramaddr(7:0)
ramdatao(7:0)
ramdatai(7:0)
ramwe
ramoe
Opcode
decoder
Program
memory
interface
External
memory
interface
Control
Unit
Internal data
memory
interface
sfraddr(6:0)
sfrdatao(7:0)
sfrdatao(7:0)
sfroe
sfrwe
User SFR’s
interface
clk
reset
rsto
I/O Port
registers
Timers
UART
Interrupt
controller
port0(7:0)
port1(7:0)
port2(7:0)
port3(7:0)
t0
t1
gate0
gate1
rxdi
rxdo
txd
int0
int1
Power
Manage-
ment Unit
DoCD™
Debug Unit
ALU
stop
pmm
tdi
tck
tms
tdo
rtck
coderun
debugacs
SXDM
interface
sxdmaddr
sxdmdatao
sxdmdatai
sxdmoe
sxdmwe
PINS DESCRIPTION
PIN TYPE
DESCRIPTION
clk input Global clock
reset
input Global reset
port0i[7:0]
input Port 0 input
port1i[7:0]
input Port 1 input
port2i[7:0]
input Port 2 input
port3i[7:0]
input Port 3 input
iprgramsize[2:0]
iprgromsize[2:0]
prgramdata[7:0]
prgromdata[7:0]
sxdmdatai[7:0]
xdatai[7:0]
input
input
input
input
input
input
Size of on-chip RAM CODE
Size of on-chip ROM CODE
Data bus from int. RAM prog. memory
Data bus from int. ROM prog. memory
Data bus from sync external data
memory (SXDM)
Data bus from external memories
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

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PIN TYPE
DESCRIPTION
ready
input External memory data ready
ramdatai[7:0]
input Data bus from internal data memory
sfrdatai[7:0]
input Data bus from user SFR’s
int0 input External interrupt 0
int1 input External interrupt 1
t0 input Timer 0 input
t1 input Timer 1 input
gate0
input Timer 0 gate input
gate1
input Timer 1 gate input
rxdi input Serial receiver input
tdi input DoCD™ TAP data input
tck input DoCD™ TAP clock input
tms input DoCD™ TAP mode select input
rsto output Reset output
port0o[7:0]
output Port 0 output
port1o[7:0]
output Port 1 output
port2o[7:0]
output Port 2 output
port3o[7:0]
output Port 3 output
prgaddr[15:0] output Internal program memory address bus
prgdatao[7:0] output Data bus for internal program memory
prgramwr
output Internal program memory write
sxdmaddr[15:0] output Sync XDATA memory address bus
(SXDM)
sxdmdatao[7:0] output Data bus for Sync XDATA memory
(SXDM)
sxdmoe
output Sync XDATA memory read (SXDM)
sxdmwe
output Sync XDATA memory write (SXDM)
xaddr[23:0]
output Address bus for external memories
xdatao[7:0]
output Data bus for external memories
xdataz
output Turn xdata bus into ‘Z’ state
xprgrd
output External program memory read
xprgwr
output External program memory write
xdatard
output External data memory read
xdatawr
output External data memory write
ramaddr[7:0]
output Internal Data Memory address bus
ramdatao[7:0] output Data bus for internal data memory
ramoe
output Internal data memory output enable
ramwe
output Internal data memory write enable
sfraddr[6:0]
output Address bus for user SFR’s
sfrdatao[7:0]
output Data bus for user SFR’s
sfroe
output User SFR’s read enable
sfrwe
output User SFR’s write enable
tdo output DoCD™ TAP data output
rtck output DoCD™ return clock line
debugacs
output DoCD™ accessing data
coderun
output CPU is executing an instruction
pmm
output Power management mode indicator
stop output Stop mode indicator
rxdo
output Serial receiver output
txd output Serial transmitter output
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are trademarks of their respective owners.
UNITS SUMMARY
ALU – Arithmetic Logic Unit performs the
arithmetic and logic operations during execu-
tion of an instruction. It contains accumulator
(ACC), Program Status Word (PSW), (B) regis-
ters and related logic such as arithmetic unit,
logic unit, multiplier and divider.
Opcode Decoder – Performs an instruction
opcode decoding and the control functions for
all other blocks.
Control Unit – Performs the core synchroniza-
tion and data flow control. This module is di-
rectly connected to Opcode Decoder and
manages execution of all microcontroller tasks.
Program Memory Interface – Contains Pro-
gram Counter (PC) and related logic. It per-
forms the instructions code fetching. Program
Memory can be also written. This feature al-
lows usage of a small boot loader loading new
program into RAM, EPROM or FLASH
EEPROM storage via UART, SPI, I2C or
DoCD™ module.
External Memory Interface - Contains mem-
ory access related registers such as Data
Page High (DPH), Data Page Low (DPL) and
Data Pointer eXtended (DPX) registers. It per-
forms the external Program and Data Memory
addressing and data transfers. Program fetch
cycle length can be programmed by user. This
feature is called Program Memory Wait States,
and allows core to work with different speed
program memories.
Synchronous eXternal Data Memory
(SXDM) Interface – contains XDATA memory
access related logic allowing fast access to
synchronous memory devices. It performs the
external Data Memory addressing and data
transfers. This memory can be used to store
large variables frequently accessed by CPU,
improving overall performance of application.
Internal Data Memory Interface – Internal
Data Memory interface controls access into the
internal 256 bytes memory. It contains 8-bit
Stack Pointer (SP) register and related logic.
User SFRs Interface – Special Function Reg-
isters interface controls access to the special
registers. It contains standard and used de-
fined registers and related logic. User defined
external devices can be quickly accessed
(read, written, modified) using all direct ad-
dressing mode instructions.
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Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.