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CAT93HC46
1K-Bit High Speed Microwire Serial EEPROM
FEATURES
s High speed operation:
– 93HC46: 3MHz
s Low power CMOS technology
s 1.8 to 6.0 volt operation
s Selectable x8 or x16 memory organization
s Self-timed write cycle with auto-clear
s Sequential Read
s Software write protection
s Power-up inadvertent write protection
s 1,000,000 program/erase cycles
s 100 year data retention
s Commercial, industrial and automotive
temperature ranges
DESCRIPTION
The CAT93HC46 is a 1K-bit Serial EEPROM memory
devices which is configured as either registers of 16 bits
(ORG pin at VCC) or 8 bits (ORG pin at GND). Each
register can be written (or read) serially by using the DI
(or DO) pin. The CAT93HC46 is manufactured using
Catalyst’s advanced CMOS EEPROM floating gate
technology. The device is designed to endure 1,000,000
program/erase cycles and has a data retention of 100
years. The CAT93HC46 is available in 8-pin DIP, 8-pin
SOIC or 8-pin TSSOP packages.
PIN CONFIGURATION
DIP Package (P)
CS 1
SK 2
DI 3
DO 4
8 VCC
7 NC
6 ORG
5 GND
SOIC Package (J) SOIC Package (S)
TSSOP Package (U)
NC
VCC
CS
SK
1
2
3
4
8 ORG CS 1
7 GND SK 2
6 DO
DI 3
5 DI
DO 4
8 VCC
7 NC
6 ORG
CS
SK
DI
5 GND DO
1
2
3
4
8
7
6
5
VCC
NC
ORG
GND
PIN FUNCTIONS
Pin Name
Function
CS Chip Select
SK Clock Input
DI Serial Data Input
DO Serial Data Output
VCC
GND
+1.8 to 6.0V Power Supply
Ground
ORG
Memory Organization
NC No Connection
PE* Program Enable
Note: When the ORG pin is connected to VCC, the X16
organization is selected. When it is connected to ground,
the X8 pin is selected. If the ORG pin is left unconnected,
then an internal pullup device will select the X16
organization.
BLOCK DIAGRAM
VCC
GND
ORG
MEMORY ARRAY
ORGANIZATION
DATA
REGISTER
DI
MODE DECODE
CS LOGIC
CLOCK
SK GENERATOR
© 2002 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
ADDRESS
DECODER
OUTPUT
BUFFER
DO
93C46/56/57/66/86 F02
Doc. No. 1008,Rev. C

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ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. 55°C to +125°C
Storage Temperature ....................... 65°C to +150°C
Voltage on any Pin with
Respect to Ground(1) ............ 2.0V to +VCC +2.0V
VCC with Respect to Ground ............... 2.0V to +7.0V
Package Power Dissipation
Capability (TA = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
RELIABILITY CHARACTERISTICS
*COMMENT
Stresses above those listed under Absolute Maximum
Ratingsmay cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Symbol
NEND(3)
TDR(3)
VZAP(3)
ILTH(3)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Min.
1,000,000
100
2000
100
Max.
Units
Cycles/Byte
Years
Volts
mA
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
D.C. OPERATING CHARACTERISTICS
(Over recommended operating conditions, unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
ICC1 Power Supply Current
(Operating Write)
3 mA fSK = 3MHz
VCC = 5.0V
ICC2 Power Supply Current
(Operating Read)
ISB1 Power Supply Current
(Standby) (x8 Mode)
500 µA fSK = 3MHz
VCC = 5.0V
10 µA CS = 0V
ORG=GND
ISB2(5)
ILI
Power Supply Current
(Standby) (x16Mode)
Input Leakage Current
(Including ORG pin)
0 µA CS=0V
ORG=Float or VCC
1 µA VIN = 0V to VCC
ILO Output Leakage Current
(Including ORG pin)
1 µA VOUT = 0V to VCC,
CS = 0V
VIL1
VIH1
VIL2
VIH2
VOL1
VOH1
VOL2
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
-0.1
2
0
VCC x 0.7
2.4
0.8
VCC + 1
VCC x 0.2
VCC + 1
0.4
0.2
V 4.5V VCC < 5.5V
V 4.5V VCC < 5.5V
V 1.8V VCC < 4.5V
V 1.8V VCC < 4.5V
V
4.5V VCC < 5.5V,
IOL=2.1mA
V 4.5V VCC < 5.5V,
IOH = -400mA
V 1.8V VCC < 4.5V, IOL=1mA
VOH2
Output High Voltage
VCC-0.2
1.8V VCC < 4.5V,
IOH = -100µA
Note:
(1) The minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from 1V to VCC +1V.
(5) Standby Current (ISB2)=0µA (<900nA).
Doc. No. 1008, Rev. C
2

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RECOMMENDED OPERATING CONDITIONS
Temperature Minimum Maximum
Commercial
0˚C
+70˚C
Industrial
-40˚C
+85˚C
Automotive
-40˚C
+105˚C
Extended
-40˚C
+125˚C
CAT93HC46
Device
CAT93HC46
CAT93HC46-1.8
Supply Voltage Range
2.5V to 6.0V
1.8V to 6.0V
PIN CAPACITANCE
Symbol
Test
COUT(1) OUTPUT CAPACITANCE (DO)
CIN(1) INPUT CAPACITANCE (CS, SK, DI, ORG)
Max.
5
5
Units
pF
pF
Conditions
VOUT=0V, TA=25˚C,
fSK=1MHz
VIN=0V, TA=25˚C, fSK=1MHz
INSTRUCTION SET
Start
Address
Instruction Bit Opcode x8
x16
READ
1 10 A6-A0 A5-A0
ERASE 1 11 A6-A0 A5-A0
WRITE 1 01 A6-A0 A5-A0
EWEN
1 00 11XXXXX 11XXXX
EWDS
1 00 00XXXXX 00XXXX
ERAL
1 00 10XXXXX 10XXXX
WRAL
1 00 01XXXXX 01XXXX
Data
x8 x16 Comments
Read Address ANA0
Clear Address ANA0
D7-D0 D15-D0 Write Address ANA0
Write Enable
Write Disable
Clear All Addresses
D7-D0 D15-D0 Write All Addresses
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
3 Doc. No. 1008, Rev. C

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POWER-UP TIMING (1)(2)
SYMBOL
tPUR
tPUW
PARAMETER
Power-up to Read Operation
Power-up to Write Operation
Max
1
1
Units
ms
ms
A.C. CHARACTERISTICS
SYMBOL PARAMETER
tCSS CS Setup Time
tCSH CS Hold Time
tDIS DI Setup Time
tDIH DI Hold Time
tPD1 Output Delay to 1
tPD0
tHZ(1)
Output Delay to 0
Output Delay to High-Z
tEW Program/Erase Pulse Width
tCSMIN
Minimum CS Low Time
tSKHI
Minimum SK High Time
tSKLOW Minimum SK Low Time
tSV Output Delay to Status Valid
SKMAX Maximum Clock Frequency
VCC =
1.8V-6V
Min. Max.
200
0
400
400
1
1
400
5
1
1
1
1
DC 250
Limits
VCC =
2.5V-6V
Min. Max.
100
0
200
200
0.5
0.5
200
5
0.5
0.5
0.5
0.5
DC 1000
VCC =
4.5V-5.5V
Test
Min. Max. UNITS Conditions
50 ns
0 ns VIL = 0.45V
50 ns VIH = 2.4V
50 ns CL = 100pF
0.1 µs VCOLL==100.08pVF
0.1 µs VOH (=3)2.0v
100 ns
5 ms
0.1 µs
0.1 µs
0.1 µs
0.1 µs CL = 100pF
DC 3000 kHz
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
(3) The input levels and timing reference points are shown in AC Test Conditionstable.
A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
50ns
0.4V to 2.4V
0.8V, 2.0V
0.2VCC to 0.7VCC
0.5VCC
4.5V VCC 5.5V
4.5V VCC 5.5V
1.8V VCC 4.5V
1.8V VCC 4.5V
Doc. No. 1008, Rev. C
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CAT93HC46
DEVICE OPERATION
The CAT93HC46 is a 1024-bit nonvolatile memory
intended for use with industry standard microprocessors.
The CAT93HC46 can be organized as either registers of
16 bits or 8 bits. When organized as X16, seven 9-bit
instructions control the reading, writing and erase
operations of the device. When organized as X8, seven
10-bit instructions control the reading, writing and erase
operations of the device. The CAT93HC46 operates on
a single power supply and will generate on chip, the high
voltage required during any write operation.
Instructions, addresses, and write data are clocked into
the DI pin on the rising edge of the clock (SK). The DO
pin is normally in a high impedance state except when
reading data from the device, or when checking the
ready/busy status after a write operation.
The ready/busy status can be determined after the start
of a write operation by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that
the device is ready for the next instruction. If necessary,
the DO pin may be placed back into a high impedance
state during chip select by shifting a dummy 1into the
DI pin. The DO pin will enter the high impedance state on
the falling edge of the clock (SK). Placing the DO pin into
the high impedance state is recommended in applications
where the DI pin and the DO pin are to be tied together
to form a common DI/O pin.
Figure 1. Sychronous Data Timing
tSKHI
SK
tDIS
DI VALID
tCSS
CS
DO
tSKLOW
VALID
tDIH
tCSH
tDIS
tPD0,tPD1
tCSMIN
DATA VALID
Figure 2a. Read Instruction Timing
SK
CS
AN AN1
DI
11
0
A0
tCS MIN
STANDBY
HIGH-Z
tPD0
DO 0
tHZ
HIGH-Z
DN DN1
D1 D0
5 Doc. No. 1008, Rev. C