70V27.pdf 데이터시트 (총 22 페이지) - 파일 다운로드 70V27 데이타시트 다운로드

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HIGH-SPEED 3.3V
32K x 16 DUAL-PORT
STATIC RAM
IDT70V27S/L
Features:
x True Dual-Ported memory cells which allow simultaneous
access of the same memory location
x High-speed access
– Industrial: 35ns (max.)
– Commercial: 15/20/25/35/55ns (max.)
www.DataSheet4xU.cLoomw-power operation
– IDT70V27S
Active: 500mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V27L
Active: 500mW (typ.)
Standby: 660µW (typ.)
x Separate upper-byte and lower-byte control for bus
matching capability
x Dual chip enables allow for depth expansion without
external logic
Functional Block Diagram
R/WL
UBL
CE0L
CE1L
OEL
LBL
x IDT70V27 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
x M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
x Busy and Interrupt Flags
x On-chip port arbitration logic
x Full on-chip hardware support of semaphore signaling
between ports
x Fully asynchronous operation from either port
x LVTTL-compatible, single 3.3V (±0.3V) power supply
x Available in 100-pin Thin Quad Flatpack (TQFP), 108-pin
Ceramic Pin Grid Array (PGA), and 144-pin Fine Pitch BGA
(fpBGA)
x Industrial temperature range (-40°C to +85°C) is available
for selected speeds
R/WR
UBR
CE0R
CE1R
OER
LBR
I/O8-15L
I/O0-7L
BUSYL (1,2)
I/O
Control
I/O
Control
A14L
A0L
Address
Decoder
A14L
A0L
CE0L
CE1L
OEL
R/WL
32Kx16
MEMORY
ARRAY
70V27
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
SEM L
NOTES:
INT
(2)
L
M/S (2)
1) BUSY is an input as a Slave (M/S=VIL) and an output as a Master (M/S=VIH).
2) BUSY and INT are non-tri-state totem-pole outputs (push-pull).
©2000 Integrated Device Technology, Inc.
6.011
Address
Decoder
A14R
A0R
CE0R
CE1R
OER
R/WR
I/O8-15R
I/O0-7R
BUSYR(1,2)
A14R
A0R
SEMR
INTR(2)
3603 drw 01
JANUARY 2001
DSC 3603/7

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IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
Commercial and Industrial Temperature Range
Description:
The IDT70V27 is a high-speed 32K x 16 Dual-Port Static RAM,
designed to be used as a stand-alone 512K-bit Dual-Port RAM or as a
combination MASTER/SLAVE Dual-Port RAM for 32-bit and wider word
systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32-
bit or wider memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.
The device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by the chip enables (CE0 and CE1) permits the on-chip
circuitry of each port to enter a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology,
thesedevicestypicallyoperateononly500mWofpower. TheIDT70V27
ispackaged in a 100-pin Thin Quad Flatpack(TQFP), a 108-pinceramic
Pin Grid Array (PGA), and a 144-pin Fine Pitch BGA (fp BGA).
www.DataSheet4PUi.cnomConfigurations(1,2,3)
INDEX
A9L
A10L
A11L
A12L
A13L
A14L
NC
NC
NC
LBL
UBL
CE0L
CE1L
SEML
Vcc
R/WL
OEL
GND
GND
I/O15L
I/O14L
I/O13L
I/O12L
I/O11L
I/O10L
1100 99 98
97 96 95
94
93 92
91 90
89 88
87
86
85 84
83 82
81
80 79
78 77
76
75
2 74
3 73
4 72
5 71
6 70
7 69
8 68
9 67
10
11
IDT70V27PF
PN100-1(4)
66
65
12 64
13
100-PIN TQFP
63
14
TOP VIEW(5)
62
15 61
16 60
17 59
18 58
19 57
20 56
21 55
22 54
23 53
24 52
25 51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A9R
A10R
A11R
A12R
A13R
A14R
NC
NC
NC
LBR
UBR
CE0R
CE1R
SEMR
GND
R/WR
OER
GND
GND
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
I/O10R
3603 drw 02
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
2

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IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
Pin Configurations(1,2,3) (con't.)
Commercial and Industrial Temperature Range
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13
NC NC A8L A5L A1L INTL GND BUSYR A1R A5R NC NC NC
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13
NC NC NC A6L A2L NC M/S INTR A2R A6R NC NC NC
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13
A10L A9L NC A7L A3L NC NC NC A3R A7R A9R A10R A11R
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13
A14L A13L A12L A11L A4L A0L BUSYL A0R A4R A8R A12R A13R A14R
www.DataSheet4U.com
E1 E2 E3 E4
LBL NC NC NC
F1 F2 F3 F4
SEML CE1L CE0L UBL
G1 G2 G3 G4
VCC VCC VCC NC
H1 H2 H3 H4
NC R/WL OEL NC
J1 J2 J3 J4
GND I/O15L I/O14L I/013L
IDT70V27BF
BF144-1(4)
144-Pin fpBGA
Top View(5)
E10 E11 E12 E13
NC NC NC LBR
F10 F11 F12 F13
UBR CE0R CE1R SEMR
G10 G11 G12 G13
NC NC GND GND
H10 H11 H12 H13
NC OER R/WR GND
J10 J11 J12 J13
I/O13R I/O14R I/O15R GND
K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13
I/O12L NC NC NC I/O6L I/O3L I/O0R I/O3R I/O6R I/O11R NC NC I/O12R
L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13
I/O11L I/O10L NC NC I/O5L I/O2L GND VCC I/O5R NC NC NC I/O10R
,
M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13
I/O9L NC NC VCC I/O4L GND I/O0L I/O2R I/O4R I/O7R I/O8R NC I/O9R
N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13
NC NC I/O8L I/O7L NC I/O1L VCC I/O1R NC VCC NC NC NC
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 12mm x 12mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
3603 drw 02a
3