128Mb MULTIBANK BURST FLASH
32Mb/64Mb ASYNC/PAGE CellularRAM COMBO
The MT28C128532W18/W30D and
MT28C128564W18/W30D combination Flash and Cel-
lularRAM are high-performance, high-density, mem-
ory solutions that can significantly improve system
performance. The Flash architecture features a multi-
partition configuration that supports READ-while-
PROGRAM/ERASE operations with no latency. A 4Mb
partition size enables optimal design flexibility.
Two Flash devices are stacked to achieve the 128Mb
density. Each Flash die has a dedicated CE# and OE#
www.DataSheceot4nUtr.coolm, enabling each Flash to be independently select-
The MT28C128532W18/W30D and
MT28C128564W18/W30D stacked Flash devices
enable soft protection for blocks, as read only, by con-
figuring soft protection registers with dedicated com-
mand sequences. For security purposes, two user-
programmable 64-bit chip protection registers are pro-
vided for each Flash device.
The embedded WORD PROGRAM and BLOCK
ERASE functions are fully automated by an on-chip
write state machine (WSM). An on-chip device status
register can be used to monitor the WSM status and
determine the progress of the PROGRAM/ERASE tasks.
Each Flash device has a read configuration register
(RCR) that defines how the Flash interacts with the mem-
ory bus. For device specifications and additional docu-
mentation concerning Flash and CellularRAM features,
please refer to the MT28F644W18/W30 data sheet at
www.micron.com/flash and the MT45W2MW16PFA and
MT45W4MW16PFA data sheets at http://
The CellularRAM architecture features high-speed
CMOS, dynamic random-access memories developed
for low-power portable applications The CellularRAM
device is available in either 32Mb or 64Mb densities.
To operate seamlessly on a burst Flash bus, Cellular-
RAM products have incorporated a transparent self-
refresh mechanism. The hidden refresh requires no
additional support from the system memory controller
and has no significant impact on device read/write per-
The refresh configuration register (CR) is used to con-
trol how refresh is performed on the DRAM array. These
registers are automatically loaded with default settings
during power-up and can be updated any time during
normal operation. Special attention has been focused
on standby current consumption during self-refresh.
CellularRAM products include three system-acces-
sible mechanisms used to minimize standby current.
Partial array refresh (PAR) limits refresh to the portion
of the memory array being used. Temperature com-
pensated refresh (TCR) is used to adjust the refresh
rate according to the ambient temperature. The
refresh rate can be decreased at lower temperatures to
minimize current consumption during standby. Deep
power down (DPD) halts the REFRESH operation alto-
gether and is used when no vital information is stored
in the device. These three refresh mechanisms are
adjusted through the CR.
Please refer to Micron’s Web site www.micron.com/
flash for the latest MT28F644W18/W30 Flash data
sheet and http://www.micron.com/cellularram for the
latest MT45W2MW16PFA and MT45W4MW16PFA Cel-
lularRAM data sheet.
Each Flash memory implements a multibank archi-
tecture (16 banks of 4Mb each) to allow concurrent
operations. Any address within a block address range
selects that block for the required READ, PROGRAM, or
Each Flash memory features eight 4K-word sectors
(8 x 65,536 bits), designated as parameter blocks, and
the remaining part is organized in main blocks of 32K
words each (524,288 bits). The parameter blocks are
addressed either by the low order addresses (bottom
boot) or by the higher order addresses (top boot).
The two Flash devices can be supplied with any
combination of top or bottom boot (e.g., top/top, bot-
tom/bottom, top/bottom, or bottom/top). Please see
Figures 2 and 3 for more information.
MT28C128564W18D_B.fm - Rev. B, Pub 7/03 EN
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.