ADVANCE
4 MEG x 16 ASYNCHRONOUS/PAGE FLASH
512K x 16 SRAM COMBO MEMORY
GENERAL DESCRIPTION
The MT28C6428P20 and MT28C6428P18 combi-
nation Flash and SRAM memory devices provide a com-
pact, low-power solution for systems where PCB real
estate is at a premium. The dual-bank Flash devices
are high-performance, high-density, nonvolatile
memory with a revolutionary architecture that can sig-
nificantly improve system performance.
This new architecture features:
• A two-memory-bank configuration supporting
dual-bank operation;
www.DataSheet4•UA.cohmigh-performance bus interface providing a fast
page data transfer; and
• A conventional asynchronous bus interface.
The devices also provide soft protection for blocks
by configuring soft protection registers with dedicated
command sequences. For security purposes, dual 64-
bit chip protection registers are provided.
The embedded WORD WRITE and BLOCK ERASE
functions are fully automated by an on-chip write state
machine (WSM). The WSM simplifies these operations
and relieves the system processor of secondary tasks.
An on-chip status register, one for each bank, can be
used to monitor the WSM status to determine the
progress of a PROGRAM/ERASE command.
The erase/program suspend functionality allows
compatibility with existing EEPROM emulation soft-
ware packages.
The devices take advantage of a dedicated power
source for the Flash memory (F_VCC) and a dedicated
power source for the SRAM (S_VCC), both at 1.70V–2.20V
for optimized power consumption and improved noise
immunity. A dedicated I/O power supply (VCCQ) is pro-
vided with an extended range (1.70V–2.20V), to allow a
direct interface to most common logic controllers and
to ensure improved noise immunity. The separate
S_VCC pin for the SRAM provides data retention capa-
bility when required. The data retention S_VCC is speci-
fied as low as 1.0V. The MT28C6428P20 and
MT28C6428P18 devices support two F_VPP voltage
ranges, an in-circuit voltage of 0.9V–2.2V and a produc-
tion compatibility voltage of 12V ±5%. The 12V ±5%
F_VPP2 is supported for a maximum of 100 cycles and 10
cumulative hours.
The MT28C6428P20 and MT28C6428P18 contain
an asynchronous 8Mb SRAM organized as 512K-words
by 16 bits. The devices are fabricated using an ad-
vanced CMOS process and high-speed/ultra-low-
power circuit technology, and then are packaged in a
67-ball FBGA package with 0.80mm pitch.
ARCHITECTURE AND MEMORY
ORGANIZATION
The Flash devices contain two separate banks of
memory (bank a and bank b) for simultaneous READ
and WRITE operations, which are available in the fol-
lowing bank segmentation configuration:
• Bank a comprises one-fourth of the memory and
contains 8 x 4K-word parameter blocks, while the
remainder of bank a is split into 31 x 32K-word
blocks.
• Bank b represents three-fourths of the memory, is
equally sectored, and contains 96 x 32K-word
blocks.
Figures 2 and 3 show the bottom and top memory
organizations.
DEVICE MARKING
Due to the size of the package, Micron’s standard
part number is not printed on the top of each device.
Instead, an abbreviated device mark comprised of a
five-digit alphanumeric code is used. The abbreviated
device marks are cross referenced to Micron part num-
bers in Table 1.
Table 1
Cross Reference for Abbreviated Device Marks
PART NUMBER
MT28C6428P20FM-80 BET
MT28C6428P20FM-80 TET
MT28C6428P18FM-85 BET
MT28C6428P18FM-85 TET
PRODUCT
MARKING
FW454
FW453
FW455
FW452
SAMPLE
MARKING
FX454
FX453
FX455
FX452
MECHANICAL
SAMPLE MARKING
FY454
FY453
FY455
FY452
4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory
MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02
2 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
