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ADVANCE
4 MEG x 16 ASYNCHRONOUS/PAGE FLASH
512K x 16 SRAM COMBO MEMORY
FLASH AND SRAM
COMBO MEMORY
MT28C6428P20
MT28C6428P18
Low Voltage, Extended Temperature
0.18µm Process Technology
FEATURES
• Flexible dual-bank architecture
• Support for true concurrent operations with no
www.DataSheetl4aUt.econmcy:
Read bank b during program bank a and vice versa
Read bank b during erase bank a and vice versa
• Organization: 4,096K x 16 (Flash)
512K x 16 (SRAM)
• Basic configuration:
Flash
Bank a (16Mb Flash for data storage)
– Eight 4K-word parameter blocks
– Thirty-one 32K-word blocks
Bank b (48Mb Flash for program storage)
– Ninety-six 32K-word main blocks
SRAM
8Mb SRAM for data storage
– 512K-words
• F_VCC, VCCQ, F_VPP, S_VCC voltages
MT28C6428P20
1.80V (MIN)/2.20V (MAX) F_VCC read voltage
1.80V (MIN)/2.20V (MAX) S_VCC read voltage
1.80V (MIN)/2.20V (MAX) VCCQ
MT28C6428P18
1.70V (MIN)/1.90V (MAX) F_VCC read voltage
1.70V (MIN)/1.90V (MAX) S_VCC read voltage
1.70V (MIN)/1.90V (MAX) VCCQ
MT28C6428P20/P18
1.80V (TYP) F_VPP (in-system PROGRAM/ERASE)
1.0V (MIN) S_VCC (SRAM data retention)
12V ±5% (HV) F_VPP (in-house programming and
accelerated programming algorithm [APA]
activation)
• Asynchronous access time
Flash access time: 80ns @ 1.80V F_VCC
SRAM access time: 80ns @ 1.80V S_VCC
• Page Mode read access
Interpage read access: 80ns @ 1.80V F_VCC
Intrapage read access: 30ns @ 1.80V F_VCC
• Low power consumption
• Enhanced suspend options
ERASE-SUSPEND-to-READ within same bank
PROGRAM-SUSPEND-to-READ within same bank
ERASE-SUSPEND-to-PROGRAM within same bank
• Read/Write SRAM during program/erase of Flash
BALL ASSIGNMENT
67-Ball FBGA (Top View)
1 2 3 4 5 6 7 8 9 10 11 12
A NC
NC A20 A11 A15 A14 A13 A12 F_VSS VccQ NC
NC
B A16 A8 A10 A9 DQ15 S_WE# DQ14 DQ7
C
F_WE# NC
A21
DQ13 DQ6 DQ4 DQ5
D VSS F_RP# DQ12 S_CE2 S_VCC F_VCC
E
F_WP# F_VPP A19 DQ11
DQ10 DQ2 DQ3
F
S_LB# S_UB# S_OE#
DQ9 DQ8 DQ0 DQ1
G
A18 A17
A7
A6
A3
A2
A1 S_CE1#
H NC NC F_VCC A5 A4 A0 F_CE# F_VSS F_OE# NC NC NC
Top View
(Ball Down)
• Dual 64-bit chip protection registers for security
purposes
• PROGRAM/ERASE cycles
100,000 WRITE/ERASE cycles per block
• Cross-compatible command set support
Extended command set
Common flash interface (CFI) compliant
OPTIONS
• Timing
80ns
85ns
• Boot Block Configuration
Top
Bottom
• Operating Voltage Range
F_VCC = 1.70V–1.90V
F_VCC = 1.80V–2.20V
• Operating Temperature Range
Commercial (0oC to +70oC)
Extended (-40oC to +85oC)
• Package
67-ball FBGA (8 x 8 grid)
MARKING
-80
-85
T
B
18
20
None
ET
FM
Part Number Example:
MT28C6428P20FM-80 BET
4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory
MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02
1
©2002, Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE
SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S
PRODUCTION DATA SHEET SPECIFICATIONS.

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ADVANCE
4 MEG x 16 ASYNCHRONOUS/PAGE FLASH
512K x 16 SRAM COMBO MEMORY
GENERAL DESCRIPTION
The MT28C6428P20 and MT28C6428P18 combi-
nation Flash and SRAM memory devices provide a com-
pact, low-power solution for systems where PCB real
estate is at a premium. The dual-bank Flash devices
are high-performance, high-density, nonvolatile
memory with a revolutionary architecture that can sig-
nificantly improve system performance.
This new architecture features:
• A two-memory-bank configuration supporting
dual-bank operation;
www.DataSheet4UA.cohmigh-performance bus interface providing a fast
page data transfer; and
• A conventional asynchronous bus interface.
The devices also provide soft protection for blocks
by configuring soft protection registers with dedicated
command sequences. For security purposes, dual 64-
bit chip protection registers are provided.
The embedded WORD WRITE and BLOCK ERASE
functions are fully automated by an on-chip write state
machine (WSM). The WSM simplifies these operations
and relieves the system processor of secondary tasks.
An on-chip status register, one for each bank, can be
used to monitor the WSM status to determine the
progress of a PROGRAM/ERASE command.
The erase/program suspend functionality allows
compatibility with existing EEPROM emulation soft-
ware packages.
The devices take advantage of a dedicated power
source for the Flash memory (F_VCC) and a dedicated
power source for the SRAM (S_VCC), both at 1.70V–2.20V
for optimized power consumption and improved noise
immunity. A dedicated I/O power supply (VCCQ) is pro-
vided with an extended range (1.70V–2.20V), to allow a
direct interface to most common logic controllers and
to ensure improved noise immunity. The separate
S_VCC pin for the SRAM provides data retention capa-
bility when required. The data retention S_VCC is speci-
fied as low as 1.0V. The MT28C6428P20 and
MT28C6428P18 devices support two F_VPP voltage
ranges, an in-circuit voltage of 0.9V–2.2V and a produc-
tion compatibility voltage of 12V ±5%. The 12V ±5%
F_VPP2 is supported for a maximum of 100 cycles and 10
cumulative hours.
The MT28C6428P20 and MT28C6428P18 contain
an asynchronous 8Mb SRAM organized as 512K-words
by 16 bits. The devices are fabricated using an ad-
vanced CMOS process and high-speed/ultra-low-
power circuit technology, and then are packaged in a
67-ball FBGA package with 0.80mm pitch.
ARCHITECTURE AND MEMORY
ORGANIZATION
The Flash devices contain two separate banks of
memory (bank a and bank b) for simultaneous READ
and WRITE operations, which are available in the fol-
lowing bank segmentation configuration:
• Bank a comprises one-fourth of the memory and
contains 8 x 4K-word parameter blocks, while the
remainder of bank a is split into 31 x 32K-word
blocks.
• Bank b represents three-fourths of the memory, is
equally sectored, and contains 96 x 32K-word
blocks.
Figures 2 and 3 show the bottom and top memory
organizations.
DEVICE MARKING
Due to the size of the package, Micron’s standard
part number is not printed on the top of each device.
Instead, an abbreviated device mark comprised of a
five-digit alphanumeric code is used. The abbreviated
device marks are cross referenced to Micron part num-
bers in Table 1.
Table 1
Cross Reference for Abbreviated Device Marks
PART NUMBER
MT28C6428P20FM-80 BET
MT28C6428P20FM-80 TET
MT28C6428P18FM-85 BET
MT28C6428P18FM-85 TET
PRODUCT
MARKING
FW454
FW453
FW455
FW452
SAMPLE
MARKING
FX454
FX453
FX455
FX452
MECHANICAL
SAMPLE MARKING
FY454
FY453
FY455
FY452
4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory
MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02
2 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.

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ADVANCE
4 MEG x 16 ASYNCHRONOUS/PAGE FLASH
512K x 16 SRAM COMBO MEMORY
PART NUMBERING INFORMATION
Micron’s low-power devices are available with sev-
eral different combinations of features (see Figure 1).
Valid combinations of features and their correspond-
ing part numbers are listed in Table 2.
Figure 1
Part Number Chart
www.DataSheet4U.com
MT 28C 642 8 P 20 FM-80 T ET
Micron Technology
Flash Family
28C = Dual-Supply Flash/SRAM Combo
Density/Organization/Banks
642 = 64Mb (4,096K x 16)
bank a = 1/4; bank b = 3/4
SRAM Density
8 = 8Mb SRAM (512K x 16)
Read Mode Operation
P = Asynchronous/Page Read
Operating Temperature Range
None = Commercial (0ºC to +70ºC)
ET = Extended (-40ºC to +85ºC)
Boot Block Starting Address
B = Bottom boot
T = Top boot
Access Time
-80 = 80ns
-85 = 85ns
Package Code
FM = 67-ball FBGA (8 x 8 grid)
Operating Voltage Range
20 = 1.80V–2.20V VCC
18 = 1.70V–1.90V
Table 2
Valid Part Number Combinations1
PART NUMBER
MT28C6428P20FM-80 BET
MT28C6428P20FM-80 TET
MT28C6428P18FM-85 BET
MT28C6428P18FM-85 TET
ACCESS
TIME (ns)
80
80
85
85
BOOT BLOCK
STARTING
ADDRESS
Bottom
Top
Bottom
Top
OPERATING
TEMPERATURE
RANGE
-40oC to +85oC
-40oC to +85oC
-40oC to +85oC
-40oC to +85oC
NOTE: 1. For part number combinations not listed in this table, please contact
your Micron representative.
4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory
MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02
3 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.

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ADVANCE
4 MEG x 16 ASYNCHRONOUS/PAGE FLASH
512K x 16 SRAM COMBO MEMORY
BLOCK DIAGRAM
www.DataSheet4U.com
F_WE#
F_OE#
F_CE#
F_RP#
A19A20
A0A18
S_CE1#
S_CE2
S_OE#
S_WE#
F_VCC
F_VPP
FLASH
Bank a
4,096K x 16
Bank b
SRAM
512K x 16
S_VCC
F_WP#
F_VSS
VCCQ
DQ0DQ15
S_VSS
S_UB#
S_LB#
F_RST#
F_CE#
F_WE#
F_OE#
DQ0-DQ15
Data Input
Buffer
CSM
WSM
I/O Logic
FLASH FUNCTIONAL BLOCK DIAGRAM
Data
Register
Program/
Erase
Pump Voltage
Generators
X DEC
Y/Z DEC
PR Lock
Query/OTP
Bank 1 Blocks
Y/Z Gating/Sensing
PR Lock
Query
OTP
Manufacturer’s ID
Device ID
Block Lock
RCR
ID Reg.
Status
Reg.
DQ0–DQ15
Output
Multiplexer
Output
Buffer
A0–A21
Address
Input
Buffer
Address
CNT/WSM
Address Latch
Address
Multiplexer
Y/Z DEC
X DEC
Y/Z Gating/Sensing
Bank 2 Blocks
4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory
MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02
4 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.

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ADVANCE
4 MEG x 16 ASYNCHRONOUS/PAGE FLASH
512K x 16 SRAM COMBO MEMORY
BALL DESCRIPTIONS
67-BALL FBGA
NUMBERS
H6, G9, G8, G7,
H5, H4, G6, G5,
B4, B6, B5, A4,
A8, A7, A6, A5,
B3, G4, G3, E5,
A3, C5
www.DataSheet4U.coHm7
SYMBOL
A0–A21
F_CE#
TYPE
Input
Input
H9 F_OE# Input
C3 F_WE# Input
D4 F_RP# Input
E3 F_WP# Input
G10 S_CE1# Input
D8 S_CE2 Input
F5 S_OE# Input
B8 S_WE# Input
F3 S_LB# Input
F4 S_UB# Input
F9, F10, E9, DQ0–DQ15 Input/
E10, C9, C10,
Output
C8, B10, F8,
F7, E8, E6, D7,
C7, B9, B7
DESCRIPTION
Address Inputs: Inputs for the addresses during READ and WRITE
operations. Addresses are internally latched during READ and WRITE
cycles. Flash: A0–A21; SRAM: A0–A18.
Flash Chip Enable: Activates the device when LOW. When CE# is HIGH,
the device is disabled and goes into standby power mode.
Flash Output Enable: Enables Flash output buffers when LOW. When
F_OE# is HIGH, the output buffers are disabled.
Flash Write Enable: Determines if a given cycle is a Flash WRITE cycle.
F_WE# is active LOW.
Reset. When F_RP# is a logic LOW, the device is in reset, which drives
the outputs to High-Z and resets the WSM. When F_RP# is a logic HIGH,
the device is in standard operation. When F_RP# transitions from logic
LOW to logic HIGH, the device resets all blocks to locked and defaults to
the read array mode.
Flash Write Protect. Controls the lock down function of the flexible
locking feature.
SRAM Chip Enable1: Activates the SRAM when it is LOW. HIGH level
deselects the SRAM and reduces the power consumption to standby
levels.
SRAM Chip Enable2: Activates the SRAM when it is HIGH. LOW level
deselects the SRAM and reduces the power consumption to standby
levels.
SRAM Output Enable: Enables SRAM output buffers when LOW. When
S_OE# is HIGH, the output buffers are disabled.
SRAM Write Enable: Determines if a given cycle is an SRAM WRITE cycle.
S_WE# is active LOW.
SRAM Lower Byte: When LOW, it selects the SRAM address lower byte
(DQ0–DQ7).
SRAM Upper Byte: When LOW, it selects the SRAM address upper byte
(DQ8–DQ15).
Data Inputs/Outputs: Input array data on the second CE# and WE#
cycle during PROGRAM command. Input commands to the command
user interface when CE# and WE# are active. Output data when CE#
and OE# are active.
(continued on next page)
4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory
MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.