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CMOS Static RAM
16K (4K x 4-Bit)
IDT6168SA
IDT6168LA
Features
x High-speed (equal access and cycle time)
– Military: 25/45ns (max.)
– Industrial: 25ns (max.)
– Commercial: 15/20/25ns (max.)
x Low power consumption
x Battery backup operation—2V data retention voltage
www.DataSheet4U(.IcDoTm6168LA only)
x Available in high-density 20-pin ceramic or plastic DIP and
20-pin leadless chip carrier (LCC)
x Produced with advanced CMOS high-performance
technology
x CMOS process virtually eliminates alpha particle
soft-error rates
x Bidirectional data input and output
x Military product compliant to MIL-STD-883, Class B
Description
The IDT6168 is a 16,384-bit high-speed static RAM organized
as 4K x 4. It is fabricated using lDT’s high-performance, high-reliability
CMOS technology. This state-of-the-art technology, combined with inno-
vative circuit design techniques, provides a cost-effective approach for
high-speed memory applications.
Access times as fast 15ns are available. The circuit also offers a
reduced power standby mode. When CS goes HIGH, the circuit will
automatically go to, and remain in, a standby mode as long as CS remains
HIGH. This capability provides significant system-level power and cooling
savings. The low-power (LA) version also offers a battery backup data
retention capability where the circuit typically consumes only 1µW
operating off a 2V battery. All inputs and outputs of the IDT6168 are
TTL-compatible and operate from a single 5V supply.
The IDT6168 is packaged in either a space saving 20-pin, 300-mil
ceramic or plastic DIP or a 20-pin LCC providing high board-level
packing densities.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.
Functional Block Diagram
A0
ADDRESS
DECODER
16,384-BIT
MEMORY ARRAY
VCC
GND
A11
I/O0
I/O CONTROL
I/O1
INPUT
DATA
I/O2 CONTROL
I/O3
,
CS
WE
©2000 Integrated Device Technology, Inc.
1
3090 drw 01
FEBRUARY 2001
DSC-3090/05

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IDT6168SA/LA
CMOS Static RAM 16K (4K x 4-Bit)
Pin Configurations
Military, Industrial, and Co mmercial Temperature Ranges
Truth Table(1)
Mode
CS WE Output
Power
A0
A1
A2
A3
A4
A5
A6
A7
www.DataSheet4U.com CS
GND
1 20 VCC
2 19 A11
3 18 A10
4 P20-1 17 A9
5
D20-1
L20-1
16 A8
6 15 I/O3
7 14 I/O2
8 13 I/O1
9 12 I/O0
,10 11 WE
3090 drw 02
DIP/LCC
Top View
Standby
Read
Write
HX
LH
LL
NOTE:
1. H = VIH, L = VIL, X = Don't Care
High-Z
DOUT
DIN
Standby
Active
Active
3090 tbl 03
Absolute Maximum Ratings(1)
Symbol
Rating
Com'l.
Mil.
VTERM
Terminal Voltage
with Respect
to GND
-0.5 to +7.0 -0.5 to +7.0
TA Operating
Temperature
0 to +70 -55 to +125
TBIAS
Temperature
Under Bias
-55 to +125 -65 to +135
Unit
V
oC
oC
TSTG Storage Temperature -55 to +125 -65 to +150 oC
Pin Descriptions
Name
A0 - A11
CS
WE
I/O0 - I/O3
Description
Address Inputs
Chip Select
Write Enable
Data Input/Output
PT Power Dissipation
1.0
1.0 W
IOUT DC Output Current
50
50 mA
NOTE:
3090 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
VCC Power
Recommended DC Operating
GND
Ground
Conditions
3090 tbl 01
Symbol
Parameter
Min. Typ. Max. Unit
VCC Supply Voltage
4.5 5.0 5.5 V
GND Ground
0 0 0V
Capacitance (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions Max. Unit
CIN Input Capacitance
VIN = 0V
7 pF
CI/O I/O Capacitance
VOUT = 0V
7 pF
VIH Input High Voltage
2.2 ____ 6.0 V
VIL Input Low Voltage
-0.5(1) ____ 0.8 V
NOTE:
3090 tbl 05
1. VIL (min.) = –3.0V for pulse width less than 20ns, once per cycle.
NOTE:
3090 tbl 02
1. This parameter is determined by device characterization, but is not production
tested.
Recommended Operating
Temperature and Supply Voltage
Grade
Temperature
GND
Vcc
Military
-55OC to +125OC 0V
5V ± 10%
Industrial
-45OC to +85OC
0V
5V ± 10%
Commercial
0OC to +70OC
0V
5V ± 10%
3090 tbl 06
2

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IDT6168SA/LA
CMOS Static RAM 16K (4K x 4-Bit)
Military, Industrial, and Co mmercial Temperature Ranges
DC Electrical Characteristics(1)
(VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V)
6168SA15
6168SA20
6168LA20
6168SA25
6168LA25
6168SA45
6168LA45
Symbol
Parameter
Power Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil.
& Ind.
Unit
ICC1 Operating Power Supply Current SA 110 ____ 90 ____ 90 100 ____ 100 mA
CS < VIL, Outputs Open
VCC = Max., f = 0(2)
LA ____ ____ 70 ____ 70 80 ____ 80
ICC2 Dynamic Operating Current
CS < VIL, Outputs Open
VCC = Max ., f = fMAX(2)
SA 145 ____ 120 ____ 110 120 ____ 110 mA
LA ____ ____ 100 ____ 90 100 ____ 80
ISB
www.DataSheet4U.com
Standby Power Supply Current
(TTL Level)
CS > VIH, Outputs Open
VCC = Max ., f = fMAX(2)
SA 55 ____ 45 ____ 35 45 ____ 35 mA
LA ____ ____ 30 ____ 25 30 ____ 25
ISB1 Full Standby Power Supply
Current (CMOS Level)
CS > VHC, VCC = Max.,
VIN < VLC or VIN > VHC, f = 0(2)
SA 20 ____ 20 ____ 3 10 ____ 10 mA
LA ____ ____ 0.5 ____ 0.5 0.3 ____ 0.3
NOTES:
1. All values are maximum guaranteed values.
2. fMAX = 1/tRC, only address inputs are cycling at fMAX. f = 0 means no address inputs are changing.
3090 tbl 07
DC Electrical Characteristics
VCC = 5.0V ± 10%
Symbol
Parameter
|ILI| Input Leakage Current
|ILO| Output Leakage Current
VOL Output LOW Voltage
VOH Output HIGH Voltage
Test Conditions
VCC = Max.,
VIN = GND to VCC
VCC = Max., CS = VIH,
VOUT = GND to VCC
IOL = 10mA, VCC = Min.
IOL = 8mA, VCC = Min.
IOH = -4mA, VCC = Min.
MIL.
COM'L.
MIL.
COM'L.
IDT6168SA
Min. Max.
____ 10
2____
____ 10
2____
____ 0.5
____ 0.4
2.4 ____
IDT6168LA
Min. Max.
5____
2____
5____
2____
____ 0.5
____ 0.4
2.4 ____
Unit
µA
µA
V
V
3090 tbl 09
6.432

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IDT6168SA/LA
CMOS Static RAM 16K (4K x 4-Bit)
Military, Industrial, and Co mmercial Temperature Ranges
Data Retention Characteristics (LA Version Only)
VLC = 0.2V, VHC = VCC – 0.2V
IDT6168LA
Symbol
Parameter
Test Condition
Min. Typ.(1) Max. Unit
VDR VCC for Data Retention
2.0 ____ V____
ICCDR Data Retention Current
CS > VHC
VIN > VHC
or < VLC
MIL.
COM'L.
____
____
____
____
0.5(2)
1.0(3)
0.5(2)
1.0(3)
100(2)
150(3)
20(2)
30(3)
µA
µA
tCDR(5)
www.DataSheett4RU(5).com
Chip Deselect to Data
Retention Time
Operation Recovery Time
0
tRC(4)
____
____
____ ns
____ ns
NOTES:
1. TA = +25°C.
2. at VCC = 2V
3. at VCC = 3V
4. tRC = Read Cycle Time.
5. This parameter is guaranteed by device characterization, but is not production tested.
3090 tbl 10
Low VCC Data Retention Waveform
DATA
RETENTION
MODE
VCC 4.5V
tCDR
VDR 2V
CS VIH VDR
4.5V
tR
VIH
,
3090 drw 03
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
5V
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
3090 tbl 11
DATA OUT
255
480
30pF*
DATAOUT
255
5V
480
5pF*
3090 drw 04
Figure 1. AC Test Load
*Includes scope and jig capacitances
4
Figure 2. AC Test Load
(for tCHZ, tCLZ, tWHZ and tOW)
3090 drw 05

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IDT6168SA/LA
CMOS Static RAM 16K (4K x 4-Bit)
Military, Industrial, and Co mmercial Temperature Ranges
AC Electrical Characteristics (VCC = 5.0V ± 10%, All Temperature Ranges)
6168SA15(1)
6168SA20(1)
6168LA20(1)
6168SA25
6168LA25
6168SA45(2)
6168LA45(2)
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle
tRC Read Cycle Time
15 ____ 20 ____ 25 ____ 45 ____ ns
tAA Address Access Time
____ 15 ____ 20 ____ 25 ____ 45 ns
tACS Chip Select Access Time
____ 15 ____ 20 ____ 25 ____ 45 ns
tCLZ(3)
Chip Select to Output in Low-Z
3 ____ 5 ____ 5 ____ 5 ____ ns
www.DataSheett4CUHZ.(3c)om
tOH
Chip Desele ct to Output in High-Z
Output Hold from Address Change
____ 8 ____ 10 ____ 10 ____ 25 ns
3 ____ 3 ____ 3 ____ 3 ____ ns
tPU(3) Chip Sele ct to Power Up Time
0 ____ 0 ____ 0 ____ 0 ____ ns
tPD(3) Chip Deselect to Power Down Time
____ 35 ____ 20 ____ 25 ____ 40 ns
NOTES:
1. 0° to +70°C temperature range only.
2. –55°C to +125°C temperature range only.
3. This parameter is guaranteed with AC Test load (Figure 2) by device characterization, but is not production tested.
3090 tbl 12
Timing Waveform of Read Cycle No. 1(1, 2)
tRC
ADDRESS
DATAOUT
tAA
tOH
PREVIOUS DATA VALID
Timing Waveform of Read Cycle No. 2(1, 3)
tRC
CS
DATAOUT
VCC
ICC
SUPPLY
CURRENT
ISB
tACS
tCLZ (4)
HIGH IMPEDANCE
tPU
NOTES:
1. WE is HIGH for Read cycle.
2. CS is LOW for Read cycle.
3. Device is continuously selected, CS is LOW.
3. Address valid prior to or coincident with CS transition LOW.
4. Transition is measured ±200mV from steady state.
6.452
DATA VALID
,3090 drw 06
tCHZ (3)
DATAOUT VALID
tPD
HIGH IMPEDANCE
3090 drw 07
,