LTC2616.pdf 데이터시트 (총 20 페이지) - 파일 다운로드 LTC2616 데이타시트 다운로드

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LTC2606/LTC2616/LTC2626
16-/14-/12-Bit Rail-to-Rail DACs
with I2C Interface
FEATURES
Smallest Pin-Compatible Single DACs:
LTC2606: 16 Bits
LTC2616: 14 Bits
LTC2626: 12 Bits
Guaranteed 16-Bit Monotonic Over Temperature
www.DataSheet24U7.cSoemlectable Addresses
400kHz I2CTM Interface
Wide 2.7V to 5.5V Supply Range
Low Power Operation: 270µA at 3V
Power Down to 1µA, Max
High Rail-to-Rail Output Drive (±15mA, Min)
Double-Buffered Data Latches
Asynchronous DAC Update Pin
LTC2606/LTC2616/LTC2626: Power-On Reset to
Zero Scale
LTC2606-1/LTC2616-1/LTC2626-1: Power-On Reset
to Midscale
Tiny (3mm × 3mm) 10-Lead DFN Package
U
APPLICATIO S
Mobile Communications
Process Control and Industrial Automation
Instrumentation
Automatic Test Equipment
DESCRIPTIO
The LTC®2606/LTC2616/LTC2626 are single 16-, 14-
and 12-bit, 2.7V-to-5.5V rail-to-rail voltage output DACs
in a 10-lead DFN package. They have built-in high perfor-
mance output buffers and are guaranteed monotonic.
These parts establish new board-density benchmarks for
16- and 14-bit DACs and advance performance standards
for output drive and load regulation in single-supply,
voltage-output DACs.
The parts use a 2-wire, I2C compatible serial interface. The
LTC2606/LTC2616/LTC2626 operate in both the standard
mode (clock rate of 100kHz) and the fast mode (clock rate
of 400kHz). An asynchronous DAC update pin (LDAC) is
also included.
The LTC2606/LTC2616/LTC2626 incorporate a power-on
reset circuit. During power-up, the voltage outputs rise less
than 10mV above zero scale; and after power-up, they stay
at zero scale until a valid write and update take place. The
power-on reset circuit resets the LTC2606-1/LTC2616-1/
LTC2626-1 to midscale. The voltage outputs stay at
midscale until a valid write and update take place.
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
BLOCK DIAGRA
SCL
3
SDA
2
I2C
INTERFACE
9
VCC
INPUT
REGISTER
CONTROL
LOGIC
6
REF
DAC
REGISTER
CA0
4
CA1
5
CA2
1
I2C
ADDRESS
DECODE
LDAC
10
GND
8
16-BIT DAC
VOUT
7
2606 BD
Differential Nonlinearity
(LTC2606)
1.0
VCC = 5V
0.8 VREF = 4.096V
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
16384
32768
CODE
49152 65535
2606 G02
26061626f
1

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LTC2606/LTC2616/LTC2626
ABSOLUTE AXI U RATI GS (Note 1)
Any Pin to GND ........................................... – 0.3V to 6V
Any Pin to VCC .............................................– 6V to 0.3V
Maximum Junction Temperature ......................... 125°C
Storage Temperature Range ................ – 65°C to 125°C
Lead Temperature (Soldering, 10 sec)................ 300°C
Operating Temperature Range:
LTC2606C/LTC2616C/LTC2626C
LTC2606-1C/LTC2616-1C/LTC2626-1C ... 0°C to 70°C
LTC2606I/LTC2616I/LTC2626I
LTC2606-1I/LTC2616-1I/LTC2626-1I .. – 40°C to 85°C
PACKAGE/ORDER I FOR ATIO
www.DataSheet4U.com
TOP VIEW
ORDER PART
NUMBER
CA2 1
SDA 2
SCL 3
CA0 4
CA1 5
10 LDAC
9 VCC
11 8 GND
7 VOUT
6 REF
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 11) IS GND
MUST BE SOLDERED TO PCB
LTC2606CDD
LTC2606IDD
LTC2606CDD-1
LTC2606IDD-1
DD PART MARKING
LAJX
LAJW
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ORDER PART
NUMBER
LTC2616CDD
LTC2616IDD
LTC2616CDD-1
LTC2616IDD-1
DD PART MARKING
LBPQ
LBPR
ORDER PART
NUMBER
LTC2626CDD
LTC2626IDD
LTC2626CDD-1
LTC2626IDD-1
DD PART MARKING
LBPS
LBPT
ELECTRICAL CHARACTERISTICS The denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), VOUT unloaded,
unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
LTC2626/LTC2626-1 LTC2616/LTC2616-1 LTC2606/LTC2606-1
MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
DC Performance
Resolution
12 14 16
Bits
Monotonicity
(Note 2)
12 14 16
Bits
DNL Differential Nonlinearity (Note 2)
±0.5
±1
±1 LSB
INL Integral Nonlinearity (Note 2)
±1 ±4
±4 ±16
±14 ±64
LSB
Load Regulation
ZSE Zero-Scale Error
VREF = VCC = 5V, Midscale
IOUT = 0mA to 15mA Sourcing
IOUT = 0mA to 15mA Sinking
VREF = VCC = 2.7V, Midscale
IOUT = 0mA to 7.5mA Sourcing
IOUT = 0mA to 7.5mA Sinking
Code = 0
0.025 0.125
0.05 0.125
0.05 0.25
0.1 0.25
19
0.1 0.5
0.2 0.5
0.2 1
0.4 1
19
0.5 2 LSB/mA
0.7 2 LSB/mA
0.9 4 LSB/mA
1.5 4 LSB/mA
19
mV
VOS Offset Error
(Note 5)
VOS Temperature
Coefficient
±1 ±9
±5
±1 ±9
±5
±1 ±9
±5
mV
µV/°C
GE Gain Error
Gain Temperature
Coefficient
±0.1 ±0.7 ±0.1 ±0.7 ±0.1 ±0.7 %FSR
±8.5 ±8.5 ±8.5 ppm/°C
2
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LTC2606/LTC2616/LTC2626
ELECTRICAL CHARACTERISTICS The denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), VOUT unloaded,
unless otherwise noted. (Note 11)
SYMBOL PARAMETER
CONDITIONS
MIN
PSR Power Supply Rejection
ROUT
DC Output Impedance
ISC Short-Circuit Output Current
VCC = ±10%
VREF = VCC = 5V, Midscale; –15mA IOUT 15mA
VREF = VCC = 2.7V, Midscale; –7.5mA IOUT 7.5mA
VCC = 5.5V, VREF = 5.5V
Code: Zero Scale; Forcing Output to VCC
Code: Full Scale; Forcing Output to GND
15
15
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VCC = 2.7V, VREF = 2.7V
Code: Zero Scale; Forcing Output to VCC
Code: Full Scale; Forcing Output to GND
7.5
7.5
Reference Input
Input Voltage Range
0
Resistance
Normal Mode
88
Capacitance
IREF Reference Current, Power Down Mode DAC Powered Down
Power Supply
VCC Positive Supply Voltage
ICC Supply Current
Digital I/O (Note 11)
For Specified Performance
VCC = 5V (Note 3)
VCC = 3V (Note 3)
DAC Powered Down (Note 3) VCC = 5V
DAC Powered Down (Note 3) VCC = 3V
2.7
VIL Low Level Input Voltage
(SDA and SCL)
–0.5
VIH High Level Input Voltage
(SDA and SCL)
(Note 8)
0.7VCC
VIL(LDAC) Low Level Input Voltage (LDAC)
VIH(LDAC) High Level Input Voltage (LDAC)
VIL(CAn) Low Level Input Voltage on CAn
(n = 0, 1, 2)
VCC = 4.5V to 5.5V
VCC = 2.7V to 5.5V
VCC = 2.7V to 5.5V
VCC = 2.7V to 3.6V
See Test Circuit 1
2.4
2.0
VIH(CAn) High Level Input Voltage on CAn
(n = 0, 1, 2)
See Test Circuit 1
0.85VCC
RINH
Resistance from CAn (n = 0, 1, 2)
See Test Circuit 2
to VCC to Set CAn = VCC
RINL
Resistance from CAn (n = 0, 1, 2)
See Test Circuit 2
to GND to Set CAn = GND
RINF
Resistance from CAn (n = 0, 1, 2)
See Test Circuit 2
to VCC or GND to Set CAn = Float
VOL Low Level Output Voltage
Sink Current = 3mA
tOF Output Fall Time
VO = VIH(MIN) to VO = VIL(MAX),
CB = 10pF to 400pF (Note 9)
tSP Pulse Width of Spikes Suppressed
by Input Filter
2
0
20 + 0.1CB
0
IIN Input Leakage
0.1VCC VIN 0.9VCC
CIN I/O Pin Capacitance
CB Capacitive Load for Each Bus Line
CCAX External Capacitive Load on Address
Pins CAn (n = 0, 1, 2)
TYP
– 81
0.05
0.06
34
36
22
29
124
15
0.001
0.340
0.27
0.35
0.10
MAX
0.15
0.15
60
60
50
50
VCC
160
1
5.5
0.5
0.4
1
1
0.3VCC
0.8
0.6
0.15VCC
10
10
0.4
250
50
1
10
400
10
UNITS
dB
mA
mA
mA
mA
V
k
pF
µA
V
mA
mA
µA
µA
V
V
V
V
V
V
V
V
k
k
M
V
ns
ns
µA
pF
pF
pF
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LTC2606/LTC2616/LTC2626
ELECTRICAL CHARACTERISTICS The denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), VOUT unloaded,
unless otherwise noted.
SYMBOL PARAMETER
AC Performance
tS Settling Time (Note 6)
Settling Time for 1LSB Step
(Note 7)
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Voltage Output Slew Rate
Capacitive Load Driving
Glitch Impulse
Multiplying Bandwidth
en Output Voltage Noise Density
Output Voltage Noise
CONDITIONS
±0.024% (±1LSB at 12 Bits)
±0.006% (±1LSB at 14 Bits)
±0.0015% (±1LSB at 16 Bits)
±0.024% (±1LSB at 12 Bits)
±0.006% (±1LSB at 14 Bits)
±0.0015% (±1LSB at 16 Bits)
At Midscale Transition
At f = 1kHz
At f = 10kHz
0.1Hz to 10Hz
LTC2626/LTC2626-1 LTC2616/LTC2616-1 LTC2606/LTC2606-1
MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
7 7 7 µs
9 9 µs
10 µs
2.7 2.7 2.7 µs
4.8 4.8 µs
5.2 µs
0.75 0.75 0.75 V/µs
1000 1000 1000 pF
12 12 12 nV • s
180 180 180 kHz
120 120 120 nV/Hz
100 100 100 nV/Hz
15 15 15 µVP-P
WU
TI I G CHARACTERISTICS The denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (See Figure 1) (Notes 10, 11)
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
VCC = 2.7V to 5.5V
fSCL SCL Clock Frequency
tHD(STA) Hold Time (Repeated) Start Condition
tLOW Low Period of the SCL Clock Pin
tHIGH High Period of the SCL Clock Pin
tSU(STA) Set-Up Time for a Repeated Start Condition
tHD(DAT) Data Hold Time
tSU(DAT) Data Set-Up Time
tr Rise Time of Both SDA and SCL Signals
tf Fall Time of Both SDA and SCL Signals
tSU(STO) Set-Up Time for Stop Condition
tBUF Bus Free Time Between a Stop and Start Condition
(Note 9)
(Note 9)
0
0.6
1.3
0.6
0.6
0
100
20 + 0.1CB
20 + 0.1CB
0.6
1.3
400 kHz
µs
µs
µs
µs
0.9 µs
ns
300 ns
300 ns
µs
µs
t1 Falling Edge of 9th Clock of the 3rd Input Byte
to LDAC High or Low Transition
400
ns
t2 LDAC Low Pulse Width
20
ns
Note 1: Absolute maximum ratings are those values beyond which the life
of a device may be impaired.
Note 2: Linearity and monotonicity are defined from code kL to code
2N – 1, where N is the resolution and kL is given by kL = 0.016(2N/VREF),
rounded to the nearest whole code. For VREF = 4.096V and N = 16, kL =
256 and linearity is defined from code 256 to code 65,535.
Note 3: Digital inputs at 0V or VCC.
Note 4: Guaranteed by design and not production tested.
Note 5: Inferred from measurement at code 256 (LTC2606/LTC2606-1),
code 64 (LTC2616/LTC2616-1) or code 16 (LTC2626/LTC2626-1) and at
full scale.
Note 6: VCC = 5V, VREF = 4.096V. DAC is stepped 1/4 scale to 3/4 scale
and 3/4 scale to 1/4 scale. Load is 2k in parallel with 200pF to GND.
Note 7: VCC = 5V, VREF = 4.096V. DAC is stepped ±1LSB between half
scale and half scale – 1. Load is 2k in parallel with 200pF to GND.
Note 8: Maximum VIH = VCC(MAX) + 0.5V
Note 9: CB = capacitance of one bus line in pF.
Note 10: All values refer to VIH(MIN) and VIL(MAX) levels.
Note 11: These specifications apply to LTC2606/LTC2606-1,
LTC2616/LTC2616-1, LTC2626/LTC2626-1.
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LTC2606/LTC2616/LTC2626
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2606
Integral Nonlinearity (INL)
32
VCC = 5V
24 VREF = 4.096V
16
8
0
www.DataSheet4U8 .com
–16
–24
–32
0
16384
32768
CODE
49152 65535
2606 G01
Differential Nonlinearity (DNL)
1.0
VCC = 5V
0.8 VREF = 4.096V
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
16384
32768
CODE
49152
65535
2606 G02
INL vs Temperature
32
VCC = 5V
24 VREF = 4.096V
16
8 INL (POS)
0
–8
INL (NEG)
–16
–24
–32
–50 –30 –10 10 30 50
TEMPERATURE (°C)
70 90
2606 G03
DNL vs Temperature
1.0
VCC = 5V
0.8 VREF = 4.096V
0.6
0.4
DNL (POS)
0.2
0
–0.2
DNL (NEG)
–0.4
–0.6
–0.8
–1.0
–50 –30 –10 10 30 50
TEMPERATURE (°C)
70 90
2606 G04
INL vs VREF
32
VCC = 5.5V
24
16
8 INL (POS)
0
–8 INL (NEG)
–16
–24
–32
0123
VREF (V)
45
2606 G05
DNL vs VREF
1.5
VCC = 5.5V
1.0
0.5
DNL (POS)
0
DNL (NEG)
–0.5
–1.0
–1.5
012345
VREF (V)
2606 G06
Settling to ±1LSB
Settling of Full-Scale Step
VOUT
100µV/DIV
SCL
2V/DIV
9TH CLOCK
OF 3RD DATA
BYTE
9.7µs
2µs/DIV
VCC = 5V, VREF = 4.096V
1/4-SCALE TO 3/4-SCALE STEP
RL = 2k, CL = 200pF
AVERAGE OF 2048 EVENTS
2606 G07
VOUT
100µV/DIV
SCR
2V/DIV
12.3µs
9TH CLOCK OF
3RD DATA BYTE
5µs/DIV
SETTLING TO ±1LSB
VCC = 5V, VREF = 4.096V
CODE 512 TO 65535 STEP
AVERAGE OF 2048 EVENTS
2606 G08
26061626f
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