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1 GSPS Direct Digital Synthesizer
AD9858
FEATURES
1 GSPS internal clock speed
Up to 2 GHz input clock (selectable divide-by-2)
Integrated 10-bit DAC
Excellent phase noise and SFDR
32-bit programmable frequency register
Simplified 8-bit parallel and SPI serial control interface
Automatic frequency sweeping capability
4 frequency profiles
3.3 V power supply
Power dissipation: 2 W typical
Integrated programmable charge pump and phase
frequency detector with fast lock circuit
Isolated charge pump supply up to 5 V
Integrated 2 GHz mixer
APPLICATIONS
VHF/UHF LO synthesis
Tuners
Instrumentation
Agile clock synthesis
Cellular base station hopping synthesizers
Radars
SONET/SDH clock synthesis
GENERAL DESCRIPTION
The AD9858 is a direct digital synthesizer (DDS) featuring a
10-bit digital-to-analog converter (DAC) operating up to 1 GSPS.
The AD9858 uses advanced DDS technology coupled with an
internal high speed, high performance DAC to form a digitally
programmable, complete high frequency synthesizer capable of
generating a frequency-agile analog output sine wave at up to
400 MHz. The AD9858 is designed to provide fast frequency
hopping and fine tuning resolution (32-bit frequency tuning
word). The frequency tuning and control words are loaded into
the AD9858 via parallel (8-bit) or serial loading formats. The
AD9858 contains an integrated charge pump (CP) and phase
frequency detector (PFD) for synthesis applications requiring
the combination of a high speed DDS along with phase-locked
loop (PLL) functions. An analog mixer is also provided on chip
for applications requiring the combination of a DDS, PLL, and
mixer, such as frequency translation loops and tuners. The AD9858
also features a divide-by-2 on the clock input, allowing the external
reference clock to be as high as 2 GHz.
The AD9858 is specified to operate over the extended industrial
temperature range of –40°C to +85°C.
DIV
DIV
PD
CP
CPISET
FUNCTIONAL BLOCK DIAGRAM
LO LO
IF IF
RF RF
÷M
÷N
CHARGE
PUMP
PHASE
DETECTOR
DIGITAL PLL
ANALOG
MULTIPLIER
FREQUENCY ACCUMULATOR
PHASE ACCUMULATOR
AD9858
32
15
15
PHASE-TO-
AMPLITUDE
10
DAC
CONVERSION
DACISET
IOUT
IOUT
14
RESET
32
32
TIMING AND CONTROL LOGIC
CONTROL REGISTERS
POWER-
DOWN
LOGIC
÷8
PS0 PS1 I/O PORT
(SER/PAR)
Figure 1.
SYSCLK
M
U
X
÷2
FUD
SYNCLK
REFCLK
REFCLK
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2003–2009 Analog Devices, Inc. All rights reserved.

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AD9858* Product Page Quick Links
Last Content Update: 11/01/2016
Comparable Parts
View a parametric search of comparable parts
Evaluation Kits
• AD9858 Evaluation Board
Documentation
Application Notes
• AN-1389: Recommended Rework Procedure for the Lead
Frame Chip Scale Package (LFCSP)
• AN-237: Choosing DACs for Direct Digital Synthesis
• AN-280: Mixed Signal Circuit Technologies
• AN-342: Analog Signal-Handling for High Speed and
Accuracy
• AN-345: Grounding for Low-and-High-Frequency Circuits
• AN-419: A Discrete, Low Phase Noise, 125 MHz Crystal
Oscillator for the AD9850
• AN-423: Amplitude Modulation of the AD9850 Direct
Digital Synthesizer
• AN-543: High Quality, All-Digital RF Frequency
Modulation Generation with the ADSP-2181 and the
AD9850 DDS
• AN-557: An Experimenter's Project:
• AN-587: Synchronizing Multiple AD9850/AD9851 DDS-
Based Synthesizers
• AN-605: Synchronizing Multiple AD9852 DDS-Based
Synthesizers
• AN-621: Programming the AD9832/AD9835
• AN-632: Provisionary Data Rates Using the AD9951 DDS
as an Agile Reference Clock for the ADN2812 Continuous-
Rate CDR
• AN-769: Generating Multiple Clock Outputs from the
AD9540
• AN-772: A Design and Manufacturing Guide for the Lead
Frame Chip Scale Package (LFCSP)
• AN-823: Direct Digital Synthesizers in Clocking
Applications Time
• AN-837: DDS-Based Clock Jitter Performance vs. DAC
Reconstruction Filter Performance
• AN-851: A WiMax Double Downconversion IF Sampling
Receiver Design
• AN-927: Determining if a Spur is Related to the DDS/DAC
or to Some Other Source (For Example, Switching
Supplies)
• AN-939: Super-Nyquist Operation of the AD9912 Yields a
High RF Output Signal
• AN-953: Direct Digital Synthesis (DDS) with a
Programmable Modulus
Data Sheet
• AD9858: 1 GSPS Direct Digital Synthesizer Data Sheet
Product Highlight
• Introducing Digital Up/Down Converters: VersaCOMM™
Reconfigurable Digital Converters

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Technical Books
• A Technical Tutorial on Digital Signal Synthesis, 1999
Tools and Simulations
• ADIsimDDS (Direct Digital Synthesis)
• AD9858 IBIS Model
Reference Designs
• CN0109
Reference Materials
Product Selection Guide
• RF Source Booklet
Technical Articles
• 400-MSample DDSs Run On Only +1.8 VDC
• ADI Buys Korean Mobile TV Chip Maker
• Basics of Designing a Digital Radio Receiver (Radio 101)
• Clock Requirements For Data Converters
• DDS Applications
• DDS Circuit Generates Precise PWM Waveforms
• DDS Design
• DDS Device Produces Sawtooth Waveform
• DDS Device Provides Amplitude Modulation
• DDS IC Initiates Synchronized Signals
• DDS IC Plus Frequency-To-Voltage Converter Make Low-
Cost DAC
• DDS Simplifies Polar Modulation
• Digital Potentiometers Vary Amplitude In DDS Devices
• Digital Up/Down Converters: VersaCOMM™ White Paper
• Digital Waveform Generator Provides Flexible Frequency
Tuning for Sensor Measurement
• Improved DDS Devices Enable Advanced Comm Systems
• Integrated DDS Chip Takes Steps To 2.7 GHz
• Simple Circuit Controls Stepper Motors
• Speedy A/Ds Demand Stable Clocks
• Synchronized Synthesizers Aid Multichannel Systems
• The Year of the Waveform Generator
• Two DDS ICs Implement Amplitude-shift Keying
• Video Portables and Cameras Get HDMI Outputs
Design Resources
• AD9858 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
Discussions
View all AD9858 EngineerZone Discussions
Sample and Buy
Visit the product page to see pricing options
Technical Support
Submit a technical question or find your regional support
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* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to
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frequently modified.

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AD9858
TABLE OF CONTENTS
Features .............................................................................................. 1 
Applications....................................................................................... 1 
General Description ......................................................................... 1 
Functional Block Diagram .............................................................. 1 
Revision History ............................................................................... 2 
Electrical Specifications ................................................................... 3 
Absolute Maximum Ratings............................................................ 6 
Thermal Performance.................................................................. 6 
Explanation of Test Levels ........................................................... 6 
ESD Caution.................................................................................. 6 
Pin Configuration and Function Descriptions............................. 7 
Typical Performance Characteristics ............................................. 9 
Theory of Operation ...................................................................... 14 
REVISION HISTORY
2/09—Rev. B to Rev. C
Changes to Features Section, General Description Section, and
Figure 1 .............................................................................................. 1
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 6
Added Thermal Performance Section ........................................... 6
Changes to Figure 3, Figure 4, and Figure 5.................................. 9
Changes to Figure 9, Figure 10 Caption, Figure 11 Caption,
Figure 13, and Figure 14 ................................................................ 10
Changes to Figure 17...................................................................... 11
Changes to Theory of Operation Section and DAC Output
Section.............................................................................................. 14
Changes to Charge Pump Section................................................ 15
Changes to Modes of Operation Section..................................... 16
Changes to Single-Tone Mode Section and Frequency Sweeping
Mode Section................................................................................... 17
Changes to SYNCLK and FUD Pins Section and Figure 33..... 18
Changes to I/O Port Functionality Section, Parallel
Programming Mode Section, and Figure 35............................... 20
Changes to Figure 36 and Serial Programming
Mode Section................................................................................... 21
Changes to Table 6.......................................................................... 22
Changes to Control Function Register (CFR) Section .............. 23
Changes to CFR[21]: Load Delta Frequency Timer Section .... 24
Changed CFR[14]: Sine/Cosine Select Bit Section to CFR[14]:
Enable Sine Output Bit Section..................................................... 24
Component Blocks..................................................................... 14 
Modes of Operation ................................................................... 16 
Synchronization.......................................................................... 18 
Programming the AD9858........................................................ 19 
Register Map ................................................................................... 22 
Register Bit Descriptions........................................................... 23 
Other Registers ........................................................................... 25 
User Profile Registers................................................................. 25 
Applications Information .............................................................. 27 
Evaluation Boards ...................................................................... 28 
Outline Dimensions ....................................................................... 29 
Warning ....................................................................................... 29 
Ordering Guide .......................................................................... 29 
Changes to Delta Frequency Tuning Word (DFTW) Section,
Delta Frequency Ramp Rate Word (DFRRW) Section, and
Phase Offset Control Section........................................................ 25
Changes to Profile Selection Section ........................................... 26
Deleted Frequency Tuning Control Section ............................... 27
Changed AD9858 Application Suggestions Section to
Applications Information Section ................................................ 27
Changes to Table 13 ....................................................................... 28
Added Exposed Paddle Notation to Outline Dimensions ........ 29
4/07—Rev. A to Rev. B
Changed EPAD to TQFP_EP............................................Universal
Updated Outline Dimensions....................................................... 31
11/03—Rev. 0 to Rev. A
Changes to Specifications.................................................................5
Moved ESD Caution to .....................................................................6
Moved Pin Configuration to............................................................7
Moved Pin Function Description to ...............................................8
Changes to Equations .................................................................... 19
Changes to Delta Frequency Ramp Rate Word (DFRRW)....... 27
4/03—Revision 0: Initial Version
Rev. C | Page 2 of 32

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AD9858
ELECTRICAL SPECIFICATIONS
Unless otherwise noted, VDD = 3.3 V ± 5%, CPVDD = 5 V ± 5%, RSET = 2 kΩ, CPISET = 2.4 kΩ, reference clock frequency = 1 GHz.
Table 1.
Parameter
REF CLOCK INPUT CHARACTERISTICS1
Reference Clock Frequency Range (Divider Off )
Reference Clock Frequency Range (Divider On)
Duty Cycle at 1 GHz
Input Capacitance
Input Impedance
Input Sensitivity
DAC OUTPUT CHARACTERISTICS
Resolution
Full-Scale Output Current
Gain Error
Output Offset
Differential Nonlinearity
Integral Nonlinearity
Output Impedance
Voltage Compliance Range
Wideband SFDR (DC to Nyquist)
26 MHz fOUT
65 MHz fOUT
126 MHz fOUT
375 MHz fOUT
180 MHz fOUT (700 MHz REFCLK)
Narrow-Band SFDR2
40 MHz fOUT (±15 MHz)
40 MHz fOUT (±1 MHz)
40 MHz fOUT (±50 kHz)
100 MHz fOUT (±15 MHz)
100 MHz fOUT (±1 MHz)
100 MHz fOUT (±50 kHz)
180 MHz fOUT (±15 MHz)
180 MHz fOUT (±1 MHz)
180 MHz fOUT (±50 kHz)
360 MHz fOUT (±15 MHz)
360 MHz fOUT (±1 MHz)
360 MHz fOUT (±50 kHz)
180 MHz fOUT (±15 MHz, 700 MHz REFCLK)
180 MHz fOUT (±1 MHz, 700 MHz REFCLK)
180 MHz fOUT (±50 kHz, (700 MHz REFCLK)
OUTPUT PHASE NOISE CHARACTERISTICS (AT 103 MHz IOUT)
At 1 kHz Offset
At 10 kHz Offset
At 100 kHz Offset
OUTPUT PHASE NOISE CHARACTERISTICS (AT 403 MHz IOUT)
At 1 kHz Offset
At 10 kHz Offset
At 100 kHz Offset
Temp Test Level Min
Typ Max
Unit
Full VI
Full VI
25°C V
25°C V
25°C IV
Full VI
10
1000
MHz
20
2000
MHz
42 50 58 %
3 pF
1500
Ω
–20 +5 dBm
Full
Full
Full VI
Full VI
Full VI
Full VI
Full VI
Full VI
10
5 20
–10
AVDD – 1.5
0.5
1
100
40
+10
15
1
1.5
AVDD + 0.5
Bits
mA
% FS
μA
LSB
LSB
V
Full V
Full V
Full V
Full V
Full IV
70
66
62
58
52
dBc
dBc
dBc
dBc
dBc
Full V
Full V
Full V
Full V
Full V
Full V
Full V
Full V
Full V
Full V
Full V
Full V
Full V
Full V
Full V
82 dBc
87 dBc
88 dBc
81 dBc
82 dBc
86 dBc
74 dBc
84 dBc
85 dBc
75 dBc
85 dBc
86 dBc
65 dBc
80 dBc
84 dBc
Full V
Full V
Full V
–147
–150
–152
dBc/Hz
dBc/Hz
dBc/Hz
Full V
Full V
Full V
–133
–137
–140
dBc/Hz
dBc/Hz
dBc/Hz
Rev. C | Page 3 of 32