IS61NLF25672.pdf 데이터시트 (총 30 페이지) - 파일 다운로드 IS61NLF25672 데이타시트 다운로드

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IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
256K x 72, 512K x 36 and 1M x 18
18Mb, FLOW THROUGH 'NO WAIT'
STATE BUS SRAM
ISSI®
AUGUST 2005
FEATURES
www.DataSheet4U1.c0o0m percent bus utilization
• No wait cycles between Read and Write
• Internal self-timed write cycle
• Individual Byte Write Control
• Single Read/Write control pin
• Clock controlled, registered address,
data and control
• Interleaved or linear burst sequence control using
MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Power Down mode
• Common data inputs and data outputs
CKE pin to enable clock and suspend operation
• JEDEC 100-pin TQFP, 165-ball PBGA and 209-
ball (x72) PBGA packages
• Power supply:
NVF: VDD 2.5V (± 5%), VDDQ 2.5V (± 5%)
NLF: VDD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%)
• JTAG Boundary Scan for PBGA packages
• Industrial temperature available
• Lead-free available
DESCRIPTION
The 18 Meg 'NLF/NVF' product family feature high-speed,
low-power synchronous static RAMs designed to provide
a burstable, high-performance, 'no wait' state, device for
networking and communications applications. They are
organized as 256K words by 72 bits, 512K words
by 36 bits and 1M words by 18 bits, fabricated with ISSI's
advanced CMOS technology.
Incorporating a 'no wait' state feature, wait cycles are
eliminated when the bus switches from read to write, or
write to read. This device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit.
All synchronous inputs pass through registers are controlled
by a positive-edge-triggered single clock input. Operations
may be suspended and all synchronous inputs ignored
when Clock Enable, CKE is HIGH. In this state the internal
device will hold their previous values.
All Read, Write and Deselect cycles are initiated by the
ADV input. When the ADV is HIGH the internal burst
counter is incremented. New external addresses can be
loaded when ADV is LOW.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock inputs and when WE is LOW.
Separate byte enables allow individual bytes to be written.
A burst mode pin (MODE) defines the order of the burst
sequence. When tied HIGH, the interleaved burst sequence
is selected. When tied LOW, the linear burst sequence is
selected.
FAST ACCESS TIME
Symbol
Parameter
6.5 7.5 Units
tKQ Clock Access Time 6.5 7.5 ns
tKC Cycle Time
7.5 8.5 ns
Frequency
133 117 MHz
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
08/26/05
1

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IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
BLOCK DIAGRAM
ISSI ®
x 72: A [0:17] or
x 36: A [0:18] or
x 18: A [0:19]
www.DataSheet4U.com
ADDRESS
REGISTER
A2-A17 or A2-A18 or A2-A19
MODE
A0-A1
BURST
ADDRESS
COUNTER
A'0-A'1
256Kx72; 512Kx36;
1024Kx18
MEMORY ARRAY
K DATA-IN
REGISTER
CLK
CKE
CONTROL
LOGIC K
CE
CE2
CE2
}ADV
WE
BWŸX
(X=a-h, a-d, or a,b)
OE
ZZ
CONTROL
REGISTER
DQx/DQPx
WRITE
ADDRESS
REGISTER
WRITE
ADDRESS
REGISTER
K DATA-IN
REGISTER
CONTROL
LOGIC
72, 36 or 18
K
BUFFER
2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
08/26/05

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IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
ISSI ®
www.DataSheet4U.com
Bottom View
209-Ball, 14 mm x 22 mm BGA
Bottom View
165-Ball, 13 mm x 15mm BGA
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
08/26/05
3

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IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
ISSI ®
PIN CONFIGURATION — 256K X 72, 209-Ball PBGA (TOP VIEW)
12345678
A DQg DQg A CE2 A ADV A CE2
B DQg DQg BWc BWg NC WE
A BWb
C DQg DQg BWh BWd NC CE NC BWe
D DQg DQg VSS NC NC OE NC NC
E DQPg DQPc VDDQ VDDQ VDD VDD VDD VDDQ
F DQc DQc VSS VSS VSS NC VSS VSS
www.DataSheGet4U.coDmQc
DQc VDDQ VDDQ
VDD
NC
VDD VDDQ
H DQc DQc VSS VSS VSS NC VSS VSS
J DQc DQc VDDQ VDDQ VDD NC VDD VDDQ
K NC
NC CLK NC
VSS CKE VSS
NC
L DQh DQh VDDQ VDDQ VDD NC VDD VDDQ
M DQh DQh VSS VSS VSS NC VSS VSS
N DQh DQh VDDQ VDDQ VDD NC VDD VDDQ
P DQh DQh VSS VSS VSS ZZ VSS VSS
R DQPd DQPh VDDQ VDDQ VDD VDD VDD VDDQ
T DQd DQd VSS NC NC MODE NC NC
U DQd DQd NC A NC A NC A
V DQd DQd A A A A1 A A
W DQd DQd TMS TDI A A0 A TDO
11 x 19 Ball BGA—14 x 22 mm2 Body—1 mm Ball Pitch
9
A
BWf
BWa
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
NC
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
NC
A
TCK
10
DQb
DQb
DQb
DQb
DQPf
DQf
DQf
DQf
DQf
NC
DQa
DQa
DQa
DQa
DQPa
DQe
DQe
DQe
DQe
11
DQb
DQb
DQb
DQb
DQPb
DQf
DQf
DQf
DQf
NC
DQa
DQa
DQa
DQa
DQPe
DQe
DQe
DQe
DQe
PIN DESCRIPTIONS
Symbol
Pin Name
A Synchronous Address Inputs
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
ADV
Synchronous Burst Address Advance
BWa-BWh
Synchronous Byte Write Enable
CE, CE2, CE2 Synchronous Chip Enable
CLK
CKE
Synchronous Clock
Clock Enable
DQx Synchronous Data Input/Output
DQPx
Parity Data I/O
VSS
MODE
OE
TCK, TDI
TDO, TMS
VDD
VDDQ
WE
ZZ
Ground
Burst Sequence Selection
Output Enable
JTAG Pins
3.3V/2.5V Power Supply
Isolated Output Buffer Supply:
3.3V/2.5V
Write Enable
Snooze Enable
4 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
08/26/05

No Preview Available !

IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
ISSI ®
PIN CONFIGURATION — 512K X 36, 165-Ball PBGA (TOP VIEW)
12345678
A NC A CE BWc BWb CE2 CKE ADV
B NC
A
CE2 BWd BWa CLK
WE
OE
9
A
A
10 11
A NC
A NC
C DQPc NC VDDQ VSS VSS VSS VSS VSS VDDQ NC DQPb
D DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
E DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
F DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
G DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
www.DataSheet4U.com
H NC VDD NC VDD VSS VSS VSS VDD NC NC ZZ
J DQd DQd VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
K DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
L DQd DQd VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
M DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
N DQPd NC
VDDQ
VSS
NC
NC
NC
VSS VDDQ NC DQPa
P NC
NC
A
A TDI A1* TDO A
A
A NC
R MODE NC
A
A TMS A0* TCK A
A
A
A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV
WE
CLK
CKE
CE
CE2
CE2
BWx (x=a-d)
Pin Name
Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address Advance/
Load
Synchronous Read/Write Control
Input
Synchronous Clock
Clock Enable
Synchronous Chip Select
Synchronous Chip Select
Synchronous Chip Select
Synchronous Byte Write Inputs
Symbol
OE
ZZ
MODE
TCK, TDI
TDO, TMS
VDD
NC
DQx
DQPx
VDDQ
VSS
Pin Name
Output Enable
Power Sleep Mode
Burst Sequence Selection
JTAG Pins
3.3V/2.5V Power Supply
No Connect
Data Inputs/Outputs
Parity Data I/O
Isolated output Power Supply
3.3V/2.5V
Ground
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
08/26/05
5