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HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Document Title
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Memory
Revision History
w w w . D a t a S h eNeot .4 U . c o m
0.0 Initial Draft
History
0.1 Renewal Product Group
0.2 Make a decision of PKG information
0.3 Append 1.8V Operation Product to Data sheet
1) Add Errata
Draft Date
Sep.17.2003
Oct.07.2003
Nov.08.2003
Dec.01.2003
Remark
Preliminary
Preliminary
Preliminary
Preliminary
tWC tWH tWP tRC tREH tRP tREA@ID Read
Specification 50 15 25 50 15 30
35
Relaxed value 60 20 40 60 20 40
45
0.4 Mar.28.2004
Preliminary
2) Modify the description of Device Operations
- /CE Don’t Care Enabled(Disabled) -> Sequential Row Read Disabled
(Enabled) (Page22)
3) Add the description of System Interface Using CE don’t care
(Page37)
1) Delete Errata
2) Change Characteristics (3V Product)
0.5 Before
After
tCRY
60 + tr
70 + tr
tREA@ID Read
35
45
Jun. 01. 2004 Preliminary
3) Delete Cache Program
1) Change TSOP1, WSOP1, FBGA package dimension
0.6 2) Edit TSOP1, WSOP1 package figures
3) Change FBGA package figure
Oct. 20. 2004
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 0.6 / Oct. 2004
1

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HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
FEATURES SUMMARY
HIGH DENSITY NAND FLASH MEMORIES
- Cost effective solutions for mass storage applications
NAND INTERFACE
- x8 or x16 bus width.
- Multiplexed Address/ Data
www.DataSheet4U-.cPoimnout compatibility for all densities
SUPPLY VOLTAGE
- 3.3V device: VCC = 2.7 to 3.6V : HY27USXX121M
- 1.8V device: VCC = 1.7 to 1.95V : HY27SSXX121M
Memory Cell Array
- 528Mbit = 528 Bytes x 32 Pages x 4,096 Blocks
PAGE SIZE
- x8 device : (512 + 16 spare) Bytes
: HY27(U/S)S08121M
- x16 device: (256 + 8 spare) Words
: HY27(U/S)S16121M
BLOCK SIZE
- x8 device: (16K + 512 spare) Bytes
- x16 device: (8K + 256 spare) Words
PAGE READ / PROGRAM
- Random access: 12us (max)
- Sequential access: 50ns (min)
- Page program time: 200us (typ)
COPY BACK PROGRAM MODE
- Fast page copy without external buffering
FAST BLOCK ERASE
- Block erase time: 2ms (Typ)
STATUS REGISTER
ELECTRONIC SIGNATURE
Sequential Row Read OPTION
AUTOMATIC PAGE 0 READ AT POWER-UP
OPTION
- Boot from NAND support
- Automatic Memory Download
SERIAL NUMBER OPTION
HARDWARE DATA PROTECTION
- Program/Erase locked during Power transitions
DATA INTEGRITY
- 100,000 Program/Erase cycles
- 10 years Data Retention
PACKAGE
- HY27US(08/16)121M-T(P)
: 48-Pin TSOP1 (12 x 20 x 1.2 mm)
- HY27US(08/16)121M-T (Lead)
- HY27US(08/16)121M-TP (Lead Free)
- HY27US08121M-V(P)
: 48-Pin WSOP1 (12 x 17 x 0.7 mm)
- HY27US08121M-V (Lead)
- HY27US08121M-VP (Lead Free)
- HY27(U/S)S(08/16)121M-F(P)
: 63-Ball FBGA (8.5 x 15 x 1.2 mm)
- HY27US(08/16)121M-F (Lead)
- HY27US(08/16)121M-FP (Lead Free)
- HY27SS(08/16)121M-F (Lead)
- HY27SS(08/16)121M-FP (Lead Free)
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 0.6 / Oct. 2004
2

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HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
DESCRIPTION
The HYNIX HY27(U/S)SXX121M series is a family of non-volatile Flash memories that use NAND cell technology. The
devices operate 3.3V and 1.8V voltage supply. The size of a Page is either 528 Bytes (512 + 16 spare) or 264 Words
(256 + 8 spare) depending on whether the device has a x8 or x16 bus width.
The address lines are multiplexed with the Data Input/ Output signals on a multiplexed x8 or x16 Input/ Output bus.
This interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint.
www.DataSheet4U.com
Each block can be programmed and erased over 100,000 cycles. To extend the lifetime of NAND Flash devices it is
strongly recommended to implement an Error Correction Code (ECC). A Write Protect pin is available to give a hard-
ware protection against program and erase operations.
The devices feature an open-drain Ready/Busy output that can be used to identify if the Program/ Erase/Read (PER)
Controller is currently active. The use of an open-drain output allows the Ready/ Busy pins from several memories to
be connected to a single pull-up resistor.
A Copy Back command is available to optimize the management of defective blocks. When a Page Program operation
fails, the data can be programmed in another page without having to resend the data to be programmed.
The devices are available in the following packages:
- 48-TSOP1 (12 x 20 x 1.2 mm)
- 48-WSOP1 (12 x 17 x 0.7 mm)
- 63-FBGA (8.5 x 15 x 1.2 mm, 6 x 8 ball array, 0.8mm pitch)
Three options are available for the NAND Flash family:
- Automatic Page 0 Read after Power-up, which allows the microcontroller to directly download the boot code from
page 0.
- Chip Enable Dont Care, which allows code to be directly downloaded by a microcontroller, as Chip Enable transitions
during the latency time do not stop the read operation.
- A Serial Number, which allows each device to be uniquely identified. The Serial Number options is subject to an NDA
(Non Disclosure Agreement) and so not described in the datasheet. For more details of this option contact your near-
est HYNIX Sales office.
Devices are shipped from the factory with Block 0 always valid and the memory content bits, in valid blocks, erased to
'1'.
Rev 0.6 / Oct. 2004
3