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Freescale Semiconductor
Data Sheet
Low-Cost 16-bit DSP with
DDR Controller and 10/100
Mbps Ethernet MAC
Document Number: MSC7113
Rev. 11, 4/2008
MSC7113
MAP-BGA–400
17 mm × 17 mm
• StarCore® SC1400 DSP extended core with one SC1400 DSP
core, 192 Kbyte of internal SRAM M1 memory, 16 way 16 Kbyte
instruction cache (ICache), four-entry write buffer, programmable
interrupt controller (PIC), and low-power Wait and Stop
processing modes.
• 8 Kbyte boot ROM.
www.DataSheAeHtB4-ULi.tceocrmossbar switch that allows parallel data transfers
between four master ports and six slave ports, where each port
connects to an AHB-Lite bus; fixed or round robin priority
programmable at each slave port; programmable bus parking at
each slave port; low power mode.
• Internal PLL generates up to 266 MHz clock for the SC1400 core
and up to 133 MHz for the crossbar switch, DMA channels, M2
memory, and other peripherals.
• Clock synthesis module provides predivision of PLL input clock;
independent clocking of the internal timers and DDR module;
programmable operation in the SC1400 low power Stop mode;
independent shutdown of different regions of the device.
• Enhanced 16-bit wide host interface (HDI16) provides a glueless
connection to industry-standard microcomputers,
microprocessors, and DSPs and can also operate with an 8-bit host
data bus, making if fully compatible with the DSP56300 HI08
from the external host side.
• DDR memory controller that supports byte enables for up to a
32-bit data bus; glueless interface to 133 MHz 14-bit page mode
DDR-RAM; 14-bit external address bus supporting up to 1 Gbyte;
and 16-bit or 32-bit external data bus.
• Programmable memory interface with independent read buffers,
programmable predictive read feature for each buffer, and a write
buffer.
• System control unit performs software watchdog timer function;
includes programmable bus time-out monitors on AHB-Lite slave
buses; includes bus error detection and programmable time-out
monitors on AHB-Lite master buses; and has address
out-of-range detection on each crossbar switch buses.
• Event port collects and counts important signal events including
DMA and interrupt requests and trigger events such as interrupts,
breakpoints, DMA transfers, or wake-up events; units operate
independently, in sequence, or triggered externally; can be used
standalone or with the OCE10.
• Multi-channel DMA controller with 32 time-multiplexed
unidirectional channels, priority-based time-multiplexing
between channels using 32 internal priority levels, fixed- or
round-robin-priority operation, major-minor loop structure, and
DONE or DRACK protocol from requesting units.
• Two independent TDM modules with independent receive and
transmit, programmable sharing of frame sync and clock,
programmable word size (8 or 16-bit), hardware-base
A-law/μ-law conversion, up to 50 Mbps data rate per TDM, up to
128 channels, with glueless interface to E1/T1 frames and MVIP,
SCAS, and H.110 buses.
• Ethernet controller with support for 10/100 Mbps MII/RMII
designed to comply with IEEE Std. 802.3™, 802.3u™, 802.3x™,
and 802.3ac™; with internal receive and transmit FIFOs and a
FIFO controller; direct access to internal memories via its own
DMA controller; full and half duplex operation; programmable
maximum frame length; virtual local area network (VLAN) tag
and priority support; retransmission of transmit FIFO following
collision; CRC generation and verification for inbound and
outbound packets; and address recognition including
promiscuous, broadcast, individual address. hash/exact match,
and multicast hash match.
• UART with full-duplex operation up to 5.0 Mbps.
• Up to 41 general-purpose input/output (GPIO) ports.
• I2C interface that allows booting from EEPROM devices up to 1
Mbyte.
• Two quad timer modules, each with sixteen configurable 16-bit
timers.
• fieldBIST™ unit detects and provides visibility into unlikely field
failures for systems with high availability to ensure structural
integrity, that the device operates at the rated speed, is free from
reliability defects, and reports diagnostics for partial or complete
device inoperability.
• Standard JTAG interface allows easy integration to system
firmware and internal on-chip emulation (OCE10) module.
• Optional booting external host via 8-bit or 16-bit access through
the HDI16, I2C, or SPI using in the boot ROM to access serial SPI
Flash/EEPROM devices; different clocking options during boot
with the PLL on or off using a variety of input frequency ranges.
© Freescale Semiconductor, Inc., 2004, 2008. All rights reserved.

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Table of Contents
1 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1 MAP-BGA Ball Layout Diagrams . . . . . . . . . . . . . . . . . .4
1.2 Signal List By Ball Location. . . . . . . . . . . . . . . . . . . . . . .6
2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.2 Recommended Operating Conditions. . . . . . . . . . . . . .18
2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .18
2.4 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .19
2.5 AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3 Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . .41
3.1 Thermal Design Considerations . . . . . . . . . . . . . . . . . .41
3.2 Power Supply Design Considerations. . . . . . . . . . . . . .42
3.3 Estimated Power Usage Calculations. . . . . . . . . . . . . .49
3.4 Reset and Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
3.5 DDR Memory System Guidelines . . . . . . . . . . . . . . . . .53
4 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
5 Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
6 Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
7 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
www.DataSLhiseteot4f UFi.gcuormes
Figure 1. MSC7113 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. MSC7113 Molded Array Process-Ball Grid Array
(MAP-BGA), Top View . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. MSC7113 Molded Array Process-Ball Grid Array
(MAP-BGA), Bottom View . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. Timing Diagram for a Reset Configuration Write . . . . 24
Figure 5. DDR DRAM Input Timing Diagram . . . . . . . . . . . . . . 24
Figure 6. DDR DRAM Output Timing Diagram . . . . . . . . . . . . . 26
Figure 7. DDR DRAM AC Test Load. . . . . . . . . . . . . . . . . . . . . 26
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
TDM Receive Signals. . . . . . . . . . . . . . . . . . . . . . . . . 27
TDM Transmit Signals . . . . . . . . . . . . . . . . . . . . . . . . 27
Ethernet Receive Signal Timing . . . . . . . . . . . . . . . . . 28
Ethernet Receive Signal Timing . . . . . . . . . . . . . . . . . 29
Asynchronous Input Signal Timing . . . . . . . . . . . . . . . 29
Serial Management Channel Timing . . . . . . . . . . . . . 30
Read Timing Diagram, Single Data Strobe . . . . . . . . 32
Read Timing Diagram, Double Data Strobe . . . . . . . . 33
Write Timing Diagram, Single Data Strobe. . . . . . . . . 33
Write Timing Diagram, Double Data Strobe . . . . . . . . 34
Host DMA Read Timing Diagram, HPCR[OAD] = 0 . . 34
Host DMA Write Timing Diagram, HPCR[OAD] = 0 . . 35
I2C Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 36
UART Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
UART Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . 37
EE Pin Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
EVNT Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
GPI/GPO Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . 38
Test Clock Input Timing Diagram . . . . . . . . . . . . . . . . 39
Boundary Scan (JTAG) Timing Diagram . . . . . . . . . . 40
Test Access Port Timing Diagram . . . . . . . . . . . . . . . 40
TRST Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . 40
Voltage Sequencing Case 1 . . . . . . . . . . . . . . . . . . . . 43
Voltage Sequencing Case 2 . . . . . . . . . . . . . . . . . . . . 44
Voltage Sequencing Case 3 . . . . . . . . . . . . . . . . . . . . 45
Voltage Sequencing Case 4 . . . . . . . . . . . . . . . . . . . . 46
Voltage Sequencing Case 5 . . . . . . . . . . . . . . . . . . . . 47
PLL Power Supply Filter Circuits . . . . . . . . . . . . . . . . 48
SSTL Termination Techniques . . . . . . . . . . . . . . . . . . 53
SSTL Power Value . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
MSC7113 Data Sheet, Rev. 11
2 Freescale Semiconductor

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JTAG Port
JTAG
DMA
(32 Channel) AMDMA
to IPBus
64
SC1400
Core
DSP
Extended
Core
Trace
Buffer
(8 KB)
Fetch
Unit
Instruction
Cache
(16 KB)
128
Extended
Core
Interface
64
AMIC
AMEC
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128 64
64
P XA XB
M1
SRAM
ASM1
(192 KB) 64
64
AMENT
Note: The arrows show the
direction of the transfer.
Ethernet
MAC
MII/RMII
ASM2
128
Boot ROM
(8 KB)
ASEMI
64 from
IPBus
External
Memory
Interface
External Bus
32
Interrupts
Interrupt Control
ASTH
64
ASAPB
32
ASIB
32
to EMI
to DMA
Host
Interface
(HDI16)
HDI16
Port
32 TDM
2 TDMs
PLL/Clock
PLL/Clock
APB I2C I2C
UART
GPIO
RS-232
GPIO
System Ctrl
32 Watchdog Events
Event Port
BTMs
to/from OCE10
IPBus
Timers
Figure 1. MSC7113 Block Diagram
Freescale Semiconductor
MSC7113 Data Sheet, Rev. 11
3

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Pin Assignments
1 Pin Assignments
This section includes diagrams of the MSC7113 package ball grid array layouts and pinout allocation tables.
1.1 MAP-BGA Ball Layout Diagrams
Top and bottom views of the MAP-BGA package are shown in Figure 2 and Figure 3 with their ball location index numbers.
Top View
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
A GND GND DQM1 DQS2 CK CK HD15 HD12 HD10 HD7 HD6 HD4 HD1 HD0 GND NC NC NC NC NC
B VDDM NC CS0 DQM2 DQS3 DQS0 CKE WE HD14 HD11 HD8 HD5 HD2 NC NC NC NC NC NC NC
C D24 D30 D25 CS1 DQM3 DQM0 DQS1 RAS CAS HD13 HD9 HD3 NC NC NC NC NC NC NC NC
D
VDDM D28
D27
GND VDDM VDDM VDDM VDDM VDDM VDDM VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDC
NC
NC
NC
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E
GND
D26
D31 VDDM VDDM VDDC VDDC VDDC VDDC VDDM VDDIO VDDIO VDDIO VDDIO VDDIO VDDC VDDC
NC
NC
NC
F
VDDM D15
D29 VDDC VDDC VDDC GND GND GND VDDM VDDM GND GND GND VDDIO VDDC VDDC
NC
NC
NC
G GND D13 GND VDDM VDDM GND GND GND GND GND GND GND GND GND VDDIO VDDIO VDDC NC NC NC
H D14 D12 D11 VDDM VDDM GND GND GND GND GND GND GND GND GND VDDIO VDDIO VDDC NC HA2 HA1
J D10 VDDM D9 VDDM VDDM VDDM GND GND GND GND GND GND GND GND GND VDDIO VDDC HA3 HACK HREQ
K D0 GND D8 VDDC VDDM GND GND GND GND GND GND GND GND GND VDDIO VDDIO VDDC HA0 HDDS HDS
L D1 GND D3 VDDC VDDM GND GND GND GND GND GND GND GND VDDIO VDDIO VDDIO VDDC HCS2 HCS1 HRW
M D2 VDDM D5 VDDM VDDM GND GND GND GND GND GND GND GND GND GND VDDC VDDC SDA UTXD URXD
N D4 D6 VREF VDDM VDDM VDDM GND GND GND GND GND GND GND GND VDDIO VDDC VDDC CLKIN SCL VSSPLL
P
D7
D17
D16 VDDM VDDM VDDM GND GND GND GND GND GND GND GND VDDIO VDDIO VDDC PORESET TPSEL VDDPLL
R
GND
D19
D18 VDDM VDDM VDDM GND VDDM GND VDDM GND GND VDDIO GND VDDIO VDDIO VDDC TDO
EE0 TEST0
T
VDDM D20
D22 VDDM VDDM VDDC VDDM VDDM VDDC VDDM VDDM VDDIO VDDIO VDDIO VDDIO VDDC VDDC MDIO TMS HRESET
U
GND
D21
D23 VDDM VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC COL TCK TRST
V VDDM NC A13 A11 A10 A5
A2 BA0 NC EVNT0 EVNT4 T0TCK T1RFS T1TD TX_ER RXD2 RXD0 TX_EN CRS TDI
W GND VDDM A12
A8
A7
A6
A3
NC EVNT1 EVNT2 T0RFS T0TFS T1RD T1TFS TXD2 RXD3 TXD1 TXCLK RX_ER MDC
Y VDDM GND A9 A1 A0 A4 BA1 NMI EVNT3 T0RCK T0RD TOTD T1RCK T1TCK TXD3 RXCLK TXD0 RXD1 GND RX_DV
Figure 2. MSC7113 Molded Array Process-Ball Grid Array (MAP-BGA), Top View
MSC7113 Data Sheet, Rev. 11
4 Freescale Semiconductor

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Pin Assignments
Bottom View
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A NC NC NC NC NC GND HD0 HD1 HD4 HD6 HD7 HD10 HD12 HD15 CK CK DQS2 DQM1 GND GND
B NC NC NC NC NC NC NC HD2 HD5 HD8 HD11 HD14 WE CKE DQS0 DQS3 DQM2 CS0 NC VDDM
C NC NC NC NC NC NC NC NC HD3 HD9 HD13 CAS RAS DQS1 DQM0 DQM3 CS1 D25 D30 D24
D
NC
NC
NC
VDD VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDM VDDM VDDM VDDM VDDM VDDM GND
D27
D28 VDDM
E
NC
NC
NC
VDD
VDD VDDIO VDDIO VDDIO VDDIO VDDIO VDDM VDD
VDD
VDD
VDD VDDM VDDM D31
D26
GND
F
NC
NC
NC
VDD
VDD VDDIO GND GND GND VDDM VDDM GND GND GND
VDD
VDD
VDD
D29 D15 VDDM
G NC NC NC VDD VDDIO VDDIO GND GND GND GND GND GND GND GND GND VDDM VDDM GND D13 GND
H HA1 HA2 NC
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J HREQ HACK HA3
VDD VDDIO VDDIO GND GND GND GND GND GND GND GND GND VDDM VDDM
VDD VDDIO GND GND GND GND GND GND GND GND GND VDDM VDDM VDDM
D11 D12 D14
D9 VDDM D10
K HDS HDDS HA0 VDD VDDIO VDDIO GND GND GND GND GND GND GND GND GND VDDM VDD D8 GND D0
L HRW HCS1 HCS2 VDD VDDIO VDDIO VDDIO GND GND GND GND GND GND GND GND VDDM VDD D3 GND D1
M URXD UTXD SDA VDD VDD GND GND GND GND GND GND GND GND GND GND VDDM VDDM D5 VDDM D2
N VSSPLL SCL CLKIN VDD
VDD VDDIO GND GND GND GND GND GND GND GND VDDM VDDM VDDM VREF
D6
D4
P VDDPLL TPSEL PORESET VDD VDDIO VDDIO GND GND GND GND GND GND GND GND VDDM VDDM VDDM D16 D17
D7
R TEST0 EE0 TDO VDD VDDIO VDDIO GND VDDIO GND GND VDDM GND VDDM GND VDDM VDDM VDDM D18 D19 GND
T HRESET TMS MDIO VDD
VDD VDDIO VDDIO VDDIO VDDIO VDDM VDDM VDD VDDM VDDM VDD VDDM VDDM D22
D20 VDDM
U TRST TCK COL VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDM D23 D21 GND
V TDI CRS TX_EN RXD0 RXD2 TX_ER T1TD T1RFS T0TCK EVNT4 EVNT0 NC BA0 A2 A5 A10 A11 A13 NC VDDM
W MDC RX_ER TXCLK TXD1 RXD3 TXD2 T1TFS T1RD T0TFS T0RFS EVNT2 EVNT1 NC A3 A6 A7 A8 A12 VDDM GND
Y RX_DV GND RXD1 TXD0 RXCLK TXD3 T1TCK T1RCK TOTD T0RD T0RCK EVNT3 NMI BA1 A4 A0 A1 A9 GND VDDM
Figure 3. MSC7113 Molded Array Process-Ball Grid Array (MAP-BGA), Bottom View
Freescale Semiconductor
MSC7113 Data Sheet, Rev. 11
5