K4H560438D-TCB3.pdf 데이터시트 (총 25 페이지) - 파일 다운로드 K4H560438D-TCB3 데이타시트 다운로드

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256Mb
Key Features
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency 2, 2.5 (clock)
www.DataShee-t4. UB.ucrosmt length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM/DM for write masking only
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 66pin TSOP II package
ORDERING INFORMATION
Part No.
K4H560438D-TC/LB3
K4H560438D-TC/LA2
K4H560438D-TC/LB0
K4H560438D-TC/LA0
K4H560838D-TC/LB3
K4H560838D-TC/LA2
K4H560838D-TC/LB0
K4H560838D-TC/LA0
K4H561638D-TC/LB3
K4H561638D-TC/LA2
K4H561638D-TC/LB0
K4H561638D-TC/LA0
Org.
64M x 4
32M x 8
16M x 16
Max Freq.
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
A0(DDR200@CL=2)
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
A0(DDR200@CL=2)
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
A0(DDR200@CL=2)
Interface
SSTL2
SSTL2
SSTL2
DDR SDRAM
Package
66pin TSOP II
66pin TSOP II
66pin TSOP II
Operating Frequencies
Speed @CL2
Speed @CL2.5
- B3(DDR333)
133MHz
166MHz
*CL : Cas Latency
- A2(DDR266A)
133MHz
133MHz
- B0(DDR266B)
100MHz
133MHz
- A0(DDR200)
100MHz
-
Rev. 0.4 May. 2002
-1-

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256Mb
Package Pinout & Dimension
DDR SDRAM
www.DataSheet4U.com
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
WE
CAS
RAS
CS
NC
BA0
BA1
AP/A10
A0
A1
A2
A3
VDD
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NC
NC
WE
CAS
RAS
CS
NC
BA0
BA1
AP/A10
A0
A1
A2
A3
VDD
VDD
NC
VDDQ
NC
DQ0
VSSQ
NC
NC
VDDQ
NC
DQ1
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NC
NC
WE
CAS
RAS
CS
NC
BA0
BA1
AP/A10
A0
A1
A2
A3
VDD
16Mb x 16
32Mb x 8
64Mb x 4
1 66
2 65
3 64
4 63
5 62
6 61
7 60
8 59
9 58
10 66 PIN TSOP(II) 57
11 (400mil x 875mil) 56
12 (0.65 mm PIN PITCH) 55
13 54
14 Bank Address
15 BA0-BA1
53
52
16
17 Row Address
18 A0-A12
51
50
49
19 48
20
Auto Precharge 47
A10
21 46
22 45
23 44
24 43
25 MS-024FC 42
26 41
27 40
28 39
29 38
30 37
31 36
32 35
33 34
256Mb package Pinout
VSS
NC
VSSQ
NC
DQ3
VDDQ
NC
NC
VSSQ
NC
DQ2
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
NC
VREF
VSS
UDM
CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
Organization
Column Address
64Mx4
A0-A9, A11
32Mx8
A0-A9
16Mx16
A0-A8
DM is internally loaded to match DQ and DQS identically.
Column address configuration
Rev. 0.4 May. 2002
-2-

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256Mb
Block Diagram (16Mbit x 4 I/O x 4 Banks)
DDR SDRAM
www.DataSheet4U.com
CK, CK
ADD
Bank Select
CK, CK
4
Data Input Register
Serial to parallel
8
8Mx8
8Mx8
8Mx8
8Mx8
8
WE
DM
4
x4
DQi
Column Decoder
Latency & Burst Length
LCKE
LRAS LCBR LWE
Programming Register
LCAS
LWCBR
Timing Register
CK, CK
DM
Data Strobe
CK, CK CKE
CS
RAS CAS
WE
DM
Rev. 0.4 May. 2002
-3-

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256Mb
Block Diagram (8Mbit x 8 I/O x 4 Banks)
DDR SDRAM
www.DataSheet4U.com
CK, CK
ADD
Bank Select
CK, CK
8
Data Input Register
Serial to parallel
WE
DM
16
4Mx16
4Mx16
4Mx16
4Mx16
16 8
x8
DQi
Column Decoder
Latency & Burst Length
LCKE
LRAS LCBR LWE
Programming Register
LCAS
LWCBR
Timing Register
CK, CK
DM
Data Strobe
CK, CK CKE
CS
RAS CAS
WE
DM
Rev. 0.4 May. 2002
-4-

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256Mb
Block Diagram (4Mbit x 16 I/O x 4 Banks)
DDR SDRAM
www.DataSheet4U.com
ADD
Bank Select
CK, CK
16
Data Input Register
Serial to parallel
LWE
LDM
32
2Mx32
2Mx32
2Mx32
2Mx32
32 16
x16
DQi
Column Decoder
Latency & Burst Length
LCKE
LRAS LCBR LWE
Programming Register
LCAS
LWCBR
Timing Register
CK, CK
LDM
Data Strobe
CK, CK CKE CS RAS CAS WE L(U)DM
Rev. 0.4 May. 2002
-5-