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RFD14N05L, RFD14N05LSM, RFP14N05L
Data Sheet
November 2004
14A, 50V, 0.100 Ohm, Logic Level,
N-Channel Power MOSFETs
These are N-channel power MOSFETs manufactured using
the MegaFET process. This process, which uses feature
sizes approaching those of LSI integrated circuits, gives
optimum utilization of silicon, resulting in outstanding
performance. They were designed for use in applications
such as switching regulators, switching converters, motor
drivers and relay drivers. This performance is accomplished
www.DataShethert4oUug.choma special gate oxide design which provides full rated
conductance at gate bias in the 3V-5V range, thereby
facilitating true on-off power control directly from logic level
(5V) integrated circuits.
Formerly developmental type TA09870.
Ordering Information
PART NUMBER
PACKAGE
BRAND
RFD14N05L
TO-251AA
14N05L
RFD14N05LSM
TO-252AA
14N05L
RFP14N05L
TO-220AB
F14N05L
NOTE: When ordering, use the entire part number. Add the suffix 9A to
obtain the TO-252AA variant in the tape and reel, i.e., RFD14N05LSM9A.
Features
• 14A, 50V
• rDS(ON) = 0.100
• Temperature Compensating PSPICE® Model
• Can be Driven Directly from CMOS, NMOS, and
TTL Circuits
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• 175oC Operating Temperature
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D
G
S
Packaging
JEDEC TO-251AA
DRAIN (FLANGE)
SOURCE
DRAIN
GATE
JEDEC TO-252AA
GATE
SOURCE
DRAIN (FLANGE)
JEDEC TO-220AB
DRAIN (FLANGE)
SOURCE
DRAIN
GATE
©2004 Fairchild Semiconductor Corporation
RFD14N05L, RFD14N05LSM, RFP14N05L Rev. B1

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RFD14N05L, RFD14N05LSM, RFP14N05L
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS
Power Dissipation . . .
Derate above 25oC
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PD
..
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg
RFD14N05L, RFD14N05LSM,
RFP14N05L
50
50
±10
14
Refer to Peak Current Curve
Refer to UIS Curve
48
0.32
-55 to 175
300
260
UNITS
V
V
V
A
W
W/oC
oC
oC
oC
www.DataSheCeAtU4TUI.OcNom: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
Electrical Specifications TC = 25oC, Unless Otherwise Specified
PARAMETER
Drain to Source Breakdown Voltage
Gate Threshold Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
Drain to Source On Resistance (Note 2)
Turn-On Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
Total Gate Charge
Gate Charge at 5V
Threshold Gate Charge
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
SYMBOL
BVDSS
VGS(TH)
IDSS
IGSS
rDS(ON)
t(ON)
td(ON)
tr
td(OFF)
tf
t(OFF)
Qg(TOT)
Qg(5)
Qg(TH)
CISS
COSS
CRSS
RθJC
RθJA
RθJA
TEST CONDITIONS
ID = 250µA, VGS = 0V, Figure 13
VGS = VDS, ID = 250µA, Figure12
VDS = 40V, VGS = 0V
VDS = 40V, VGS = 0V, TC = 150oC
VGS = ±10V
ID = 14A, VGS = 5V, Figures 9, 11
VDD = 25V, ID = 7A,
RL = 3.57, VGS = 5V,
RGS = 0.6
VGS = 0V to 10V
VGS = 0V to 5V
VGS = 0V to 1V
VDD = 40V, ID = 14A,
RL = 2.86
Figures 20, 21
VDS = 25V, VGS = 0V, f = 1MHz
Figure 14
TO-251 and TO-252
TO-220
MIN
50
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Source to Drain Diode Specifications
TYP
-
-
-
-
-
-
-
13
24
42
16
-
-
-
-
670
185
50
-
-
-
MAX
-
2
1
50
±100
0.100
60
-
-
-
-
100
40
25
1.5
-
-
-
3.125
100
80
UNITS
V
V
µA
µA
nA
ns
ns
ns
ns
ns
ns
nC
nC
nC
pF
pF
pF
oC/W
oC/W
oC/W
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
Source to Drain Diode Voltage (Note 2)
VSD ISD = 14A
- - 1.5 V
Diode Reverse Recovery Time
trr ISD = 14A, dISD/dt = 100A/µs
- - 125 ns
NOTES:
2. Pulse Test: Pulse Width 300ms, Duty Cycle 2%.
3. Repetitive Rating: Pulse Width limited by max junction temperature. See Transient Thermal Impedance Curve (Figure 3) and Peak Current
Capability Curve (Figure 5).
©2004 Fairchild Semiconductor Corporation
RFD14N05L, RFD14N05LSM, RFP14N05L Rev. B1

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RFD14N05L, RFD14N05LSM, RFP14N05L
Typical Performance Curves Unless Otherwise Specified
1.2
1.0
0.8
0.6
0.4
0.2
www.DataSheet4U.com
0
0 25 50 75 100 125 150 175
TC, CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
16
12
8
4
0
25 50
75 100 125 150 175
TC, CASE TEMPERATURE (oC)
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE
2
1
0.5
0.2
0.1
0.1
0.05
0.02
0.01
SINGLE PULSE
0.01
10-5
10-4
PDM
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
10-3
10-2
10-1
t, RECTANGULAR PULSE DURATION (s)
100
101
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
100 TC = 25oC
TJ = MAX. RATED
100µs
10
1ms
1
0.5
1
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
10ms
100ms
DC
100
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
©2004 Fairchild Semiconductor Corporation
200
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
100
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
I = I25 175 - TC
150
10 TC = 25oC
10-5
10-4
VGS = 5V
VGS = 10V
10-3
10-2
10-1
t, PULSE WIDTH (s)
100
FIGURE 5. PEAK CURRENT CAPABILITY
101
RFD14N05L, RFD14N05LSM, RFP14N05L Rev. B1

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RFD14N05L, RFD14N05LSM, RFP14N05L
Typical Performance Curves Unless Otherwise Specified (Continued)
50
STARTING TJ = 25oC
10
STARTING TJ = 150oC
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS-VDD) +1]
www.DataSheet4U1.com
0.01
0.1
1
tAV, TIME IN AVALANCHE (ms)
10
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
35
VGS = 10V
30
25
20
15
10
VGS = 5V
VGS = 4.5V
VGS = 4V
PULSE DURATION = 80µs, TC = 25oC
DUTY CYCLE = 0.5% MAX.
VGS = 3V
5 VGS = 2.5V
0
0 1.5 3.0 4.5 6.0 7.5
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 7. SATURATION CHARACTERISTICS
35
-55oC
30
25oC
175oC
25
20
15
10
PULSE DURATION = 80µs
5 DUTY CYCLE = 0.5% MAX.
VDD = 15V
0
0 1.5 3.0 4.5 6.0 7.5
VGS, GATE TO SOURCE VOLTAGE (V)
FIGURE 8. TRANSFER CHARACTERISTICS
250
ID = 7A ID = 14A
ID = 28A
200
150
100 ID = 3.5A
50
0
2.5
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.
3.0 3.5 4.0 4.5
VGS, GATE TO SOURCE VOLTAGE (V)
5.0
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
160
VDD = 25V, ID = 14A, RL = 3.57
140
td(OFF)
120
100 tr
80
tf
60
40
20
0
0
td(ON)
10 20 30 40
RGS, GATE TO SOURCE RESISTANCE ()
50
FIGURE 10. SWITCHING TIME vs GATE RESISTANCE
2.5
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.
2.0 VGS = 10V, ID = 14A
1.5
1.0
0.5
0
-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
©2004 Fairchild Semiconductor Corporation
RFD14N05L, RFD14N05LSM, RFP14N05L Rev. B1

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RFD14N05L, RFD14N05LSM, RFP14N05L
Typical Performance Curves Unless Otherwise Specified (Continued)
2.0
VGS = VDS, ID = 250µA
1.5
2.0
ID = 250µA
1.5
1.0 1.0
0.5
www.DataSheet4U.co0m
-80
-40 0
40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)
200
FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
800
600
400
200
0
0
CISS
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS CDS + CGD
COSS
CRSS
5 10 15 20
VDS, DRAIN TO SOURCE VOLTAGE (V)
25
FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
Test Circuits and Waveforms
VARY tP TO OBTAIN
REQUIRED PEAK IAS
VGS
tP
0V
RG
VDS
L
DUT
+
VDD
-
IAS
0.01
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT
©2004 Fairchild Semiconductor Corporation
0.5
0
-80 -40
0
40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
50
VDD = BVDSS
40
VDD = BVDSS
5
4
30 3
20 0.75 BVDSS
0.50 BVDSS
0.25 BVDSS
2
10 RL = 3.57
IG(REF) = 0.4mA
VGS = 5V
1
00
20 I-I-G-G-----((--AR-----CE----F-T---)-)
t, TIME (µs)
80 I-I-G-G-----((--AR-----CE----F-T---)-)
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260,
FIGURE 15. TRANSCONDUCTANCE vs DRAIN CURRENT
tP
IAS
BVDSS
VDS
VDD
0
tAV
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
RFD14N05L, RFD14N05LSM, RFP14N05L Rev. B1