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PS22053
MITMSUITBSIUSBHISSHEIMSIECMOINCDOUNCDTUOCRTO<RDu<aDl-uIna-lL-Iinn-eLiPnaecPkacgkeaIgneteIlnlitgeellnigtePnotwPeorwMeor dMuoled>ule>
PS22PS02523053
TRATNRSAFNESRF-EMRO-MLDOLTDYPTEYPE
INSIUNLSAUTLEADTETDYPTEYPE
INTEGRATED POWER FUNCTIONS
1200V/10A low-loss 4th generation IGBT inverter bridge
for 3 phase DC-to-AC power conversion
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INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS
• For upper-leg IGBTS :Drive circuit, High voltage high-speed level shifting, Control supply under-voltage (UV) protection.
• For lower-leg IGBTS : Drive circuit, Control supply under-voltage protection (UV), Short circuit protection (SC).
• Fault signaling : Corresponding to an SC fault (Lower-side IGBT) or a UV fault (Lower-side supply).
• Input interface : 5V line CMOS/TTL compatible (High active logic).
APPLICATION
AC400V 0.2kW~0.75kW inverter drive for small power motor control.
Fig. 1 PACKAGE OUTLINES
Dimensions in mm
2.54±0.3
302.54(=76.2)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
Type name , Lot No.
2-φ4.5±0.2
QR
Code
22 23 24 25 26 27 28
8±0.3
10.16±0.3
67±0.3
79±0.5
Heat sink side
A
(2.5)
Heat sink side
(2)
Detail : A
All external terminals are treated with lead free solder (ingredient : Sn-Cu) plating.
1. VUFS
2. VUFB
3. VP1
4. UP
5. VVFS
6. VVFB
7. VP1
8. VP
9. VWFS
10. VWFB
11. VP1
12. VPC
13. WP
14. VN1
15. VNC
16. CIN
17. CFO
18. FO
19. UN
20. VN
21. WN
22. P
23. U
24. V
25. W
26. NU
27. NV
28. NW
May 2005

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MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS22053
TRANSFER-MOLD TYPE
INSULATED TYPE
Fig. 2 INTERNAL FUNCTIONS BLOCK DIAGRAM (TYPICAL APPLICATION EXAMPLE)
www.DataSheet4U.com
C1 : Tight tolerance, temp-compensated electrolytic type
(Note : The capacitance depends on the PWM control
scheme used in the applied system.)
C2 : 0.22~2µF R-category ceramic capacitor for noise filtering
Inrush current
limiter circuit
High-side input (PWM)
(5V line) (Note 1,2)
Input signal Input signal Input signal
conditioning conditioning conditioning
Level shifter Level shifter Level shifter
Protection
circuit (UV)
Protection
circuit (UV)
Protection
circuit (UV)
Drive circuit Drive circuit Drive circuit
P
C2
C1
(Note 6)
DIP-IPM
AC line input
C
Z
(Note 4)
NU
(Note 8) NV
NW
N1 VNC
CIN
H-side IGBTS
U
V
W
L-side IGBTS
M
AC line output
Z : ZNR (Surge absorber)
C : AC filter (Ceramic capacitor 2.2~6.5nF)
(Protection against common-mode noise)
Input signal conditioning
Fo logic
Drive circuit
Protection
circuit
Low-side input (PWM)
FO CFO
(5V line) (Note 1, 2) Fault output (5V line)
(Note 3, 5)
Control supply
Under-Voltage
protection (UV)
(Note 7)
VNC
VD
(15V line)
Note1:
2:
3:
4:
5:
6:
7:
8:
To prevent input signals oscillation, an RC coupling at each input terminal is recommended.
By virtue of integrating HVIC inside the module, direct coupling to MCU terminals without any opto-coupler or transformer isolation is possible.
Fo output is open drain type. The signal line should be pulled up to the positive side of a 5V supply with an approximate 10kresistor.
The wiring between the power DC-link capacitor and the P/N1 terminals should be as short as possible to protect DIP-IPM against catastrophic high
surge voltage. For extra precaution, a small film type snubber capacitor (0.1~0.22µF, high voltage type) is recommended to mount closely to the
P and N1 terminals.
Fo output pulse width (tFO) should be determined by connecting external capacitor between CFO and VNC terminals. (Example : tFO=2.4ms(typ.)
at CFO=22nF)
High voltage (1200V or more) and fast recovery type (less than 100ns) diodes should be used for the bootstrap circuit.
It is recommended to insert a Zener diode (24V/1W) between each pair of control supply terminals to prevent surge destruction.
To prevent LVIC from surge destruction, it is recommended to mount a fast recovery type diode between VNC and NU, NV, NW terminals.
Fig. 3 EXTERNAL PART OF THE DIP-IPM PROTECTION CIRCUIT
DIP-IPM
Drive circuit
P
IC (A)
SC protection
trip level
H-side IGBTS
External protection circuit
N1
Shunt
resistor
A
(Note 1)
R
C
B
L-side IGBTS
NU
NV
NW
CIN
Drive circuit
U
V
W
Note1:
2:
C VNC
(Note 2)
Protection circuit
In the recommended external protection circuit, please select the RC time
constant in the range 1.5~2.0µs.
To prevent erroneous protection operation, the wiring of A, B, C should be
as short as possible.
Collector current
waveform
0
2
tw (µs)
Short Circuit Protective Function (SC) :
SC protection is achieved by sensing the L-side DC-Bus current (through the external
shunt resistor) with a suitable filtering time (defined by the RC circuit).
When the sensed shunt voltage exceeds the SC trip-level, all the L-side IGBTs are turned
OFF and a fault signal (Fo) is output.
Since the SC fault may be repetitive, it is recommended to stop the system and check the fault,
when the Fo signal is received.
May 2005

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MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS22053
TRANSFER-MOLD TYPE
INSULATED TYPE
MAXIMUM RATINGS (Tj = 25°C, unless otherwise noted)
INVERTER PART
Symbol
Parameter
Condition
Ratings
Unit
VCC
VCC(surge)
VCES
±IC
±ICP
PC
www.DataSheet4UT.cj om
Supply voltage
Supply voltage (surge)
Collector-emitter voltage
Each IGBT collector current
Each IGBT collector current (peak)
Collector dissipation
Junction temperature
Applied between P-NU, NV, NW
Applied between P-NU, NV, NW
TC = 25°C
TC = 25°C, less than 1ms
TC = 25°C, per 1 chip
(Note 1)
900
1000
1200
10
20
50.0
20~+125
V
V
V
A
A
W
°C
Note 1 : The maximum junction temperature rating of the power chips integrated within the DIP-IPM is 150°C (@ TC 100°C) however, to en-
sure safe operation of the DIP-IPM, the average junction temperature should be limited to Tj(ave) 125°C (@ TC 100°C).
CONTROL (PROTECTION) PART
Symbol
Parameter
VD Control supply voltage
VDB Control supply voltage
VIN Input voltage
VFO Fault output supply voltage
IFO Fault output current
VSC Current sensing input voltage
Condition
Applied between VP1-VPC, VN1-VNC
Applied between VUFB-VUFS, VVFB-VVFS,
VWFB-VWFS
Applied between UP, VP, WP-VPC,
UN, VN, WN-VNC
Applied between FO-VNC
Sink current at FO terminal
Applied between CIN-VNC
Ratings
20
20
0.5~VD+0.5
0.5~VD+0.5
1
0.5~VD+0.5
Unit
V
V
V
V
mA
V
TOTAL SYSTEM
Symbol
Parameter
VCC(PROT)
Self protection supply voltage limit
(short circuit protection capability)
TC Module case operation temperature
Tstg Storage temperature
Viso Isolation voltage
Condition
VD = 13.5~16.5V, Inverter part
Tj = 125°C, non-repetitive, less than 2 µs
(Note 2)
60Hz, Sinusoidal, AC 1 minute, connection
pins to heat-sink plate
Ratings
800
20~+100
40~+125
2500
Unit
V
°C
°C
Vrms
Note 2 : TC MEASUREMENT POINT
Control terminals
Heat sink boundary
Power terminals TC
Heat-sink
TC
May 2005

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MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS22053
TRANSFER-MOLD TYPE
INSULATED TYPE
THERMAL RESISTANCE
Symbol
Parameter
Condition
Limits
Min. Typ. Max. Unit
Rth(j-c)Q
Rth(j-c)F
Junction to case thermal
resistance
Inverter IGBT part (per 1/6 module)
Inverter FWDi part (per 1/6 module)
— — 2.00 °C/W
— — 2.67 °C/W
Rth(c-f) Contact thermal resistance (Note 3) Case to fin, (per 1 module) thermal grease applied
— — 0.047 °C/W
Note 3: Grease with good thermal conductivity and long-term endurance should be applied evenly with about +100µm~+200µm on the con-
tacting surface of DIP-IPM and heat-sink.
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ELECTRICAL CHARACTERISTICS (Tj = 25°C, unless otherwise noted)
INVERTER PART
Symbol
Parameter
VCE(sat)
VEC
ton
trr
tc(on)
toff
tc(off)
ICES
Collector-emitter saturation
voltage
FWDi forward voltage
Switching times
Collector-emitter cut-off
current
Condition
VD = VDB = 15V
VIN = 5V, IC = 10A
IC = 10A, VIN = 0V
Tj = 25°C
Tj = 125°C
VCC = 600V, VD = VDB = 15V
IC = 10A, Tj = 125°C, VIN = 0 5V
Inductive load (upper-lower arm)
VCE = VCES
Tj = 25°C
Tj = 125°C
Limits
Unit
Min. Typ. Max.
2.7 3.4
2.5 3.2 V
2.5 3.0 V
0.8 1.5 2.2 µs
0.2 µs
0.4 0.7 µs
2.8 3.8 µs
0.4 0.7 µs
——
1
mA
— — 10
CONTROL (PROTECTION) PART
Symbol
Parameter
Condition
Limits
Unit
Min. Typ. Max.
ID Circuit current
VD = VDB = 15V
VIN = 5V
VD = VDB = 15V
Total of VP1-VPC, VN1-VNC
VUFB-VUFS, VVFB-VVFS, VWFB-VWFS
Total of VP1-VPC, VN1-VNC
3.70 mA
1.30 mA
3.50 mA
VIN = 0V
VUFB-VUFS, VVFB-VVFS, VWFB-VWFS
1.30 mA
VFOH
VFOL
Fault output voltage
VSC = 0V, FO circuit pull-up to 5V with 10k
VSC = 1V, IFO = 1mA
4.9 — — V
1.10
V
VSC(ref) Short circuit trip level
Tj = 25°C, VD = 15V
(Note 4)
0.43
0.48
0.53
V
IIN Input current
VIN = 5V
0.7 1.5 2.0 mA
UVDBt
Trip level
10.0
12.0
V
UVDBr
UVDt
Supply circuit under-voltage
protection
Tj 125°C
Reset level
Trip level
10.5
12.5
V
10.3
12.5
V
UVDr
Reset level
10.8
13.0
V
tFO Fault output pulse width CFO = 22nF
(Note 5)
1.6
2.4
ms
Vth(on)
Vth(off)
ON threshold voltage
OFF threshold voltage
Applied between UP, VP, WP-VPC, UN, VN, WN-VNC
2.0 3.0 4.2 V
0.8 1.4 2.0 V
Note 4 : Short circuit protection is functioning only at the low-arms. Please select the value of the external shunt resistor such that the SC trip-
level is less than 1.7 times device current rating.
5 : Fault signal is output when the low-arms short circuit or control supply under-voltage protective functions operate. The fault output pulse-
width tFO depends on the capacitance value of CFO according to the following approximate equation : CFO = 9.3 10-6 tFO [F].
May 2005

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MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS22053
TRANSFER-MOLD TYPE
INSULATED TYPE
MECHANICAL CHARACTERISTICS AND RATINGS
Parameter
Mounting torque
Weight
Heat-sink flatness
Condition
Mounting screw : M4
Recommended 1.18 N·m
(Note 6)
Min.
0.98
50
Limits
Typ.
77
Max.
1.47
100
Unit
N·m
g
µm
www.DataSheet4UN.ocotem6: Measurement point of heat-sink flatness
+
Heat-sink side
Measurement location
3.25mm
+
Heat-sink side
RECOMMENDED OPERATION CONDITIONS
Symbol
Parameter
Condition
Limits
Min. Typ.
VCC Supply voltage
VD Control supply voltage
VDB Control supply voltage
VD, VDB Control supply variation
tdead
Arm shoot-through blocking time
fPWM
PWM input frequency
IO Output r.m.s. current
PWIN(on)
Applied between P-NU, NV, NW
Applied between VP1-VPC, VN1-VNC
Applied between VUFB-VUFS, VVFB-VVFS, VWFB-VWFS
For each input signal, TC 100°C
TC 100°C, Tj 125°C
VCC = 600V, VD = 15V, fC = 15kHz
P.F = 0.8, sinusoidal PWM
Tj 125°C, TC 100°C
(Note 7)
(Note 8)
350
13.5
13.5
1
3.3
1.5
600
15.0
15.0
350 VCC 800V,
13.5 VD 16.5V,
Ic 10A
2.5
Minimum input pulse width
PWIN(off)
13.5 VDB 16.5V,
20°C TC 100°C,
N line wiring inductance less than
10 < Ic 17A
2.7
10nH
(Note 9)
VNC VNC variation
Between VNC-NU, NV, NW (including surge)
5.0
Note 7 : The output r.m.s. current value depends on the actual application conditions.
8 : DIP-IPM might not make response to the input on signal with pulse width less than PWIN (on).
9 : DIP-IPM might not make response or work properly if the input off signal pulse width is less than PWIN (off).
Max.
800
16.5
16.5
1
15
3.4
5.0
Unit
V
V
V
V/µs
µs
kHz
Arms
µs
V
May 2005