80C85AHRS.pdf 데이터시트 (총 29 페이지) - 파일 다운로드 80C85AHRS 데이타시트 다운로드

No Preview Available !

E2O0009-27-X2
¡ Semiconductor¡ Semiconductor
MTShMis8v0eCrs8i5oAn:HJRaSn./G19S9/8JS
Previous version: Aug. 1996
MSM80C85AHRS/GS/JS
8-Bit CMOS MICROPROCESSOR
GENRAL DESCRIPTION
The MSM80C85AH is a complete 8-bit parallel; central processor implemented in silicon gate
C-MOS technology and compatible with MSM80C85A.
It is designed with higher processing speed (max.5 MHz) and lower power consumption
compared with MSM80C85A and power down mode is provided, thereby offering a high level
of system integration.
www.DataSheTeth4Ue.McomSM80C85AH uses a multiplexed address/data bus. The address is split between the 8-
bit address bus and the 8-bit data bus. The on-chip address latch : of a MSM81C55-5 memory
product allows a direct interface with the MSM80C85AH.
FEATURES
• Power down mode (HALT-HOLD)
• Low Power Dissipation: 50mW(Typ)
• Single + 3 to + 6 V Power Supply
• –40 to + 85°C, Operating Temperature
• Compatible with MSM80C85A
• 0.8 ms instruction Cycle (VCC = 5V)
• On-Chip Clock Generator (with External Crystal)
• On-Chip System Controller; Advanced Cycle Status Information Available for Large System
Control
• Bug operation in MSM80C85AH is fixed
• Four Vectored interrupt (One is non-maskable) Plus the 8080A-compatible interrupt.
• Serial, In/Serial Out Port
• Decimal, Binary and Double Precision Arithmetic
• Addressing Capability to 64K Bytes of Memory
• TTL Compatible
• 40-pin Plastic DIP(DIP40-P-600-2.54): (Product name: MSM80C85AHRS)
• 44-pin Plastic QFJ(QFJ44-P-S650-1.27): (Product name: MSM80C85AHJS)
• 44-pin Plastic QFP(QFP44-P-910-0.80-2K): (Product name: MSM80C85AHGS-2K)
1/29

No Preview Available !

¡ Semiconductor
FUNCTIONAL BLOCK DIAGRAM
INTR INTA
RST
5.5 6.5 7.5 TRAP
MSM80C85AHRS/GS/JS
SID SOD
Interrupt Control
8-Bit Internal Data Bus
Serial I/O Control
Accumulator
(8)
www.DataSheet4U.com
Temporary Register
(8)
Flag (5)
Flip Flops
Arithmetic
Logic Unit
ALU(8)
Power
Supply
+5V
GND
Power Down
Timing And Control
X1 CLK
X2 GEN
Control
Status
DMA
Instruction
Register (8)
Instruction
Decoder
And
Machine
Cycle
Encoding
Reset
B REG (8)
C REG (8)
D REG (8)
E REG (8)
H REG (8)
C REG (8)
Stack Pointer (16)
Program Counter (16)
Incrementer/Decrementer
Address Latch (16)
Register
Array
Address Buffer (8)
Data/Address
Buffer (8)
CLK READY RD WR ALE S0 S1 IO / M HOLD HLDA RESET IN RESET OUT
OUT
A15 - A8
Address Bus
AD7 - AD0
Address/Data Bus
2/29

No Preview Available !

¡ Semiconductor
MSM80C85AHRS/GS/JS
PIN CONFIGURATION (TOP VIEW)
40 pin Plastic DIP
www.DataSheet4U.com
44 pin Plastic QFP
X1 1
X2 2
RESET OUT 3
SOD 4
SID 5
TRAP 6
RST7.5 7
RST6.5 8
RST5.5 9
INTR 10
INTA 11
AD0 12
AD1 13
AD2 14
AD3 15
AD4 16
AD5 17
AD6 18
AD7 19
GND 20
40 VCC
39 HOLD
38 HLDA
37 CLK(OUT)
36 RESET IN
35 READY
34 IO/M
33 S1
32 RD
31 WR
30 ALE
29 S0
28 A15
27 A14
26 A13
25 A12
24 A11
23 A10
22 A9
21 A8
TRAP 1
RST7.5 2
RST6.5 3
RST5.5 4
INTR 5
INTA 6
AD0 7
AD1 8
AD2 9
AD3 10
NC 11
33 READY
32 IO/M
31 S1
30 RD
29 WR
28 ALE
27 S0
26 A15
25 A14
24 A13
23 A12
44 pin Plastic QFJ
TRAP 7
RST7.5 8
RST6.5 9
RST5.5 10
INTR 11
NC 12
INTA 13
AD0 14
AD1 15
AD2 16
AD3 17
39 READY
38 IO/M
37 S1
36 RD
35 WR
34 NC
33 ALE
32 S0
31 A15
30 A14
29 A13
3/29