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74 Series GHz Logic
PO74G126A
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
02/07/07
FEATURES:
DESCRIPTION:
. Patented technology
. Operating frequency up to 1.125GHz with 2pf load
. Operating frequency up to 700MHz with 5pf load
www.DataSheet4U.com . Operating frequency up to 400MHz with 15pf load
. VCC Operates from 1.65V to 3.6V
. Propagation delay < 1.5ns max with 15pf load
. Low input capacitance: 4pf typical
. Available in 14pin 150mil wide SOIC package
Potato Semiconductor’s PO74G126A is designed for
world top performance using submicron CMOS
technology to achieve 1.125GHz TTL /CMOS output
frequency with less than 1.5ns propagation delay.
This quadruple bus buffer gate is designed for 1.65-V
to 3.6-V VCC operation.
The PO74G126A featuresindependent
linedriverswith3-stateoutputs. Eachoutput isdisabled-
whenthe associatedoutput-enable(OE)input islow.
Inputs can be driven from either 3.3V or 5V devices.
This feature allows the use of these devices as
translators in a mixed 3.3V/5V system environment.
Pin Configuration
1OE
1A
1Y
2OE
2A
2Y
GND
1
2
3
4
5
6
7
14 V C C
13 4OE
12 4A
11 4Y
10 3OE
9 3A
8 3Y
Pin Description
INPUTS
OE A
HH
HL
LX
OUTPUT
Y
H
L
Z
Logic Block Diagram
1
1OE
1A 2
4
2OE
2A 5
3 1Y
6 2Y
10
3OE
3A 9
13
4OE
4A 12
8 3Y
11 4Y
1
Copyright © Potato Semiconductor Corporation

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74 Series GHz Logic
PO74G126A
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
02/07/07
Maximum Ratings
Description
Max
Storage Temperature
www.DataSheet4U.com Operation Temperature
-65 to 150
-40 to 85
Operation Voltage
-0.5 to +4.6
Input Voltage
-0.5 to +5.5
Output Voltage
-0.5 to Vcc+0.5
Unit
°C
°C
V
V
V
Note:
stresses greater than listed under
Maximum Ratings may cause
permanent damage to the device. This
is a stress rating only and functional
operation of the device at these or any
other conditions above those indicated
in the operational sections of this
specification is not implied. Exposure
to absolute maximum rating conditions
for extended periods may affect
reliability specification is not implied.
DC Electrical Characteristics
Symbol
Description
Test Conditions
VOH
VOL
VIH
VIL
IIH
IIL
VIK
Output High voltage Vcc=3V Vin=VIH or VIL, IOH= -12mA
Output Low voltage Vcc=3V Vin=VIH or VIL, IOH=12mA
Input High voltage Guaranteed Logic HIGH Level (Input Pin)
Input Low voltage
Guaranteed Logic LOW Level (Input Pin)
Input High current Vcc = 3.6V and Vin = 5.5V
Input Low current
Vcc = 3.6V and Vin = 0V
Clamp diode voltage Vcc = Min. And IIN = -18mA
Min Typ Max
2.4 3 -
- 0.3 0.5
2 - 5.5
-0.5 - 0.8
--1
- - -1
- -0.7 -1.2
Unit
V
V
V
V
uA
uA
V
Notes:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 3.3V, 25 °C ambient.
3. This parameter is guaranteed but not tested.
4. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
5. VoH = Vcc – 0.6V at rated current
2
Copyright © Potato Semiconductor Corporation

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74 Series GHz Logic
PO74G126A
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
02/07/07
Power Supply Characteristics
Symbol
Description
Test Conditions (1)
Min Typ Max Unit
IccQ Quiescent Power Supply Current
Vcc=Max, Vin=Vcc or GND -
0.1 30 uA
www.DataSheet4U.com Icc Power Supply Current per Input High Vcc=Max, Vin= Vcc-0.6V
- 50 300 uA
Notes:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 3.3V, 25°C ambient.
3. This parameter is guaranteed but not tested.
4. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
5. VoH = Vcc – 0.6V at rated current
Capacitance
Parameters (1)
Cin
Cout
Description
Input Capacitance
Output Capacitance
Test Conditions
Vin = 0V
Vout = 0V
Notes:
1 This parameter is determined by device characterization but not production tested.
Typ Unit
4 pF
6 pF
Switching Characteristics
Symbol
tPLH
tPHL
tPZH or tPZL
Description
Propagation Delay A to Y
Propagation Delay A to Y
Output Enable Time
tPHZ or tPLZ Output Disable Time
tr/tf
fmax
fmax
fmax
Rise/Fall Time
Input Frequency
Input Frequency
Input Frequency
Test Conditions (1)
CL = 15pF
CL = 15pF
CL = 15pF
CL = 15pF
0.8V – 2.0V
CL =15pF
CL = 5pF
CL = 2pF
Max
1.5
1.5
2.5
2.5
0.8
400
750
1125
Notes:
1. See test circuits and waveforms.
2. tpLH, tpHL, tsk(p), and tsk(o) are production tested. All other parameters guaranteed but not production tested.
3. Airflow of 1m/s is recommended for frequencies above 133MHz
Unit
ns
ns
ns
ns
ns
MHz
MHz
MHz
3
Copyright © 2005-2006, Potato Semiconductor Corporation

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74 Series GHz Logic
PO74G126A
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
02/07/07
Test Waveforms
www.DataSheet4U.com
Test Circuit
50
15pF
to
2pF
50
500
500
4
Copyright © Potato Semiconductor Corporation

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74 Series GHz Logic
PO74G126A
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
02/07/07
Packaging Mechanical Drawing: 14 pin 150mil SOIC
www.DataSheet4U.com
0.244 6.20
0.228 5.80
0.010
0.007
0.25
0.17
0.050 1.27
0.016 0.40
X.XX Denotes dimensions in inches
X.XX
X.XX
X.XX
Denotes dimensions in millimenters
5
Copyright © Potato Semiconductor Corporation