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12-Bit, 170 MSPS/210 MSPS/250 MSPS,
1.8 V Analog-to-Digital Converter
AD9626
FEATURES
SNR = 64.8 dBFS @ fIN up to 70 MHz @ 250 MSPS
ENOB of 10.5 @ fIN up to 70 MHz @ 250 MSPS (−1.0 dBFS)
SFDR = 80 dBc @ fIN up to 70 MHz @ 250 MSPS (−1.0 dBFS)
Excellent linearity
DNL = ±0.3 LSB typical
INL = ±0.7 LSB typical
www.DataSheeCt4MUO.cSomoutputs
Single data port at up to 250 MHz
Interleaved dual port @ ½ sample rate up to 125 MHz
700 MHz full power analog bandwidth
On-chip reference, no external decoupling required
Integrated input buffer and track-and-hold
Low power dissipation
272 mW @ 170 MSPS
364 mW @ 250 MSPS
Programmable input voltage range
1.0 V to 1.5 V, 1.25 V nominal
1.8 V analog and digital supply operation
Selectable output data format (offset binary, twos
complement, Gray code)
Clock duty cycle stabilizer
Integrated data capture clock
GENERAL DESCRIPTION
The AD9626 is a 12-bit monolithic sampling analog-to-digital
converter optimized for high performance, low power, and ease
of use. The product operates at up to a 250 MSPS conversion
rate and is optimized for outstanding dynamic performance in
wideband carrier and broadband systems. All necessary func-
tions, including a track-and-hold (T/H) and voltage reference,
are included on the chip to provide a complete signal
conversion solution.
The ADC requires a 1.8 V analog voltage supply and a differen-
tial clock for full performance operation. The digital outputs are
CMOS compatible and support either twos complement, offset
binary format, or Gray code. A data clock output is available for
proper output data timing.
Fabricated on an advanced CMOS process, the AD9626 is
available in a 56-lead LFCSP, specified over the industrial
temperature range (−40°C to +85°C).
APPLICATIONS
Wireless and wired broadband communications
Cable reverse path
Communications test equipment
Radar and satellite subsystems
Power amplifier linearization
FUNCTIONAL BLOCK DIAGRAM
RBIAS PWDN
AGND
AVDD (1.8V)
CML
VIN+
VIN–
CLK+
CLK–
REFERENCE
AD9626
TRACK-AND-HOLD
CLOCK
MANAGEMENT
ADC 12
12-BIT
CORE
SERIAL PORT
OUTPUT 12
STAGING
LVDS
RESET SCLK SDIO CSB
Figure 1.
DRVDD
DRGND
Dx11 TO Dx0
OVRA
OVRB
DCO+
DCO–
PRODUCT HIGHLIGHTS
1. High Performance—Maintains 64.9 dBFS SNR @ 250 MSPS
with a 70 MHz input.
2. Low Power—Consumes only 364 mW @ 250 MSPS.
3. Ease of Use—CMOS output data and output clock signal
allow interface to current FPGA technology. The on-chip
reference and sample-and-hold provide flexibility in
system design. Use of a single 1.8 V supply simplifies
system power supply design.
4. Serial Port Control—Standard serial port interface supports
various product functions, such as data formatting, clock
duty cycle stabilizer, power-down, gain adjust, and output
test pattern generation.
5. Pin-Compatible Family—10-bit pin-compatible family
offered as the AD9601.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.

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AD9626
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
DC Specifications ......................................................................... 3
www.DataShAeeCt4SUp.eccoimfications.......................................................................... 4
Digital Specifications ................................................................... 5
Switching Specifications .............................................................. 6
Timing Diagrams.......................................................................... 7
Absolute Maximum Ratings............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution.................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Equivalent Circuits ......................................................................... 11
Typical Performance Characteristics ........................................... 12
Theory of Operation ...................................................................... 18
Analog Input and Voltage Reference ....................................... 18
REVISION HISTORY
11/07—Revision 0: Initial Version
Clock Input Considerations...................................................... 19
Power Dissipation and Power-Down Mode ........................... 20
Digital Outputs ........................................................................... 20
Timing—Single Port Mode ....................................................... 21
Timing—Interleaved Mode....................................................... 21
Layout Considerations................................................................... 22
Power and Ground Recommendations ................................... 22
CML ............................................................................................. 22
RBIAS........................................................................................... 22
AD9626 Configuration Using the SPI ..................................... 22
Hardware Interface..................................................................... 23
Configuration Without the SPI ................................................ 23
Memory Map .................................................................................. 25
Reading the Memory Map Table.............................................. 25
Reserved Locations .................................................................... 25
Default Values ............................................................................. 25
Logic Levels................................................................................. 25
Evaluation Board ............................................................................ 27
Outline Dimensions ....................................................................... 33
Ordering Guide .......................................................................... 33
Rev. 0 | Page 2 of 36

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AD9626
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, single port output mode, DCS enabled,
unless otherwise noted.
Table 1.
Parameter1
RESOLUTION
ACCURACY
No Missing Codes
www.DataSheet4UO.fcfosemt Error
Gain Error
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
Gain Error
ANALOG INPUTS (VIN+, VIN−)
Differential Input Voltage Range2
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
POWER SUPPLY
AVDD
DRVDD
Supply Currents
IAVDD 3
IDRVDD3/Single Port Mode4
IDRVDD3/Interleaved Mode5
Power Dissipation3
Single Port Mode4
Interleaved Mode5
Power-Down Mode Supply
Currents
IAVDD
IDRVDD
Standby Mode Supply Currents
IAVDD
IDRVDD
Temp
AD9626-170
Min Typ Max
12
Full Guaranteed
25°C 4.0
Full −12
+12
25°C 1.4
Full −2.1
+4.5
25°C 0.3
Full −0.6
+0.6
25°C 0.7
Full −1.4
+1.4
Full ±8
Full 0.021
Full 0.98 1.25 1.5
Full 1.4
Full 4.3
25°C 2
Full 1.7
1.8
Full 1.58 1.8
1.9
1.9
Full 134 143
Full 17 18.5
Full 15
Full
Full 272 291
Full 268
Full 40
Full 170
Full 19
Full 170
AD9626-210
Min Typ Max
12
Guaranteed
4.0
−12 +12
1.4
−2.1 +4.5
0.3
−0.6 +0.6
0.6
−1.1 +1.1
±8
0.021
0.98 1.25 1.5
1.4
4.3
2
1.7 1.8 1.9
1.7 1.8 1.9
151 161
21 22
18
310 330
304
40
170 22
19
170 22
AD9626-250
Min Typ Max
12
Guaranteed
4.0
−12 +12
1.4
−2.1 +4.5
0.3
−0.6 +0.6
0.7
−1.7 +1.7
±8
0.021
0.98 1.25 1.5
1.4
4.3
2
1.7 1.8 1.9
1.7 1.8 1.9
178 191
24 25.5
20
364 390
357
40
170
19
170
Unit
Bits
mV
mV
% FS
% FS
LSB
LSB
LSB
LSB
μV/°C
%/°C
V p-p
V
pF
V
V
mA
mA
mA
mW
mW
mW
μA
μA
mA
μA
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2 The input range is programmable through the SPI, and the range specified reflects the nominal values of each setting. See the Memory Map section.
3 IAVDD and IDRVDD are measured with a −1 dBFS, 10.3 MHz sine input at rated sample rate.
4 Single data rate mode; this is the default mode of the AD9626.
5 Interleaved mode; user-programmable feature. See the Memory Map section.
Rev. 0 | Page 3 of 36

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AD9626
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, , Single Port Output mode, DCS
enabled, unless otherwise noted.1
Table 2.
Parameter2
SNR
fIN = 10 MHz
fIN = 70 MHz
www.DataSSIhNeAeDt4U.com
fIN = 10 MHz
fIN = 70 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 10 MHz
fIN = 70 MHz
WORST HARMONIC (SECOND OR THIRD)
fIN = 10 MHz
fIN = 70 MHz
WORST OTHER (SFDR EXCLUDING
SECOND AND THIRD)
fIN = 10 MHz
fIN = 70 MHz
TWO-TONE IMD
140.2 MHz/141.3 MHz @ −7 dBFS
170.2 MHz/171.3 MHz @ −7 dBFS
ANALOG INPUT BANDWIDTH
Temp
25°C
Full
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
25°C
Full
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
25°C
AD9626-170
Min Typ Max
64.5
63.6
64.4
63.0
64.5
63.5
64.2
62.6
10.6
10.5
84
75
79
71
92
85
92
81
80
700
AD9626-210
Min Typ Max
64.4
63.0
64.2
62.3
64.4
62.8
64.0
62.0
10.6
10.5
86
77
79
73
90
79
87
77
83
700
AD9626-250
Min Typ Max
64.0
63.8
64.0
63.4
10.5
10.5
83
73
80
71
84
76
84
73
83
700
Unit
dB
dB
dB
dB
dB
dB
dB
dB
Bits
Bits
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBFS
dBc
MHz
1 All ac specifications tested by driving CLK+ and CLK− differentially.
2 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
Rev. 0 | Page 4 of 36

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AD9626
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.
Table 3.
Parameter1
CLOCK INPUTS
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Temp
Full
Full
Full
Full
www.DataSheet4UIn.cpoumt Common-Mode Range
High Level Input Voltage (VIH)
Low Level Input Voltage (VIL)
Input Resistance (Differential)
Input Capacitance
LOGIC INPUTS
Logic 1 Voltage
Full
Full
Full
Full
Full
Full
Logic 0 Voltage
Full
Logic 1 Input Current (SDIO)
Logic 0 Input Current (SDIO)
Logic 1 Input Current
(SCLK, PDWN, CSB, RESET)
Logic 0 Input Current
(SCLK, PDWN, CSB, RESET)
Input Capacitance
LOGIC OUTPUTS2
High Level Output Voltage
Low Level Output Voltage
Output Coding
Full
Full
Full
Full
25°C
Full
Full
AD9626-170
Min Typ Max
AD9626-210
Min Typ Max
AD9626-250
Min Typ Max
CMOS/LVDS/LVPECL
1.2
0.2 6
AVDD −
0.3
AVDD +
1.6
1.1 AVDD
1.2 3.6
0 0.8
16 20 24
4
CMOS/LVDS/LVPECL
1.2
0.2 6
AVDD −
0.3
AVDD +
1.6
1.1 AVDD
1.2 3.6
0 0.8
16 20 24
4
CMOS/LVDS/LVPECL
1.2
0.2 6
AVDD −
0.3
AVDD +
1.6
1.1 AVDD
1.2 3.6
0 0.8
16 20 24
4
0.8 ×
AVDD
0.2 ×
AVDD
0
−60
55
0
4
0.8 ×
AVDD
0.8 ×
AVDD
0.2 ×
AVDD
0
−60
55
0
4
0.2 ×
AVDD
0
−60
50
0
4
DRVDD − 0.05
DRVDD − 0.05
DRVDD − 0.05
GND + 0.05
GND + 0.05
GND + 0.05
Twos complement, Gray code, or offset binary (default)
Unit
V
V p-p
V
V
V
V
pF
V
V
μA
μA
μA
μA
pF
V
V
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2 LVDS RTERMINATION = 100 Ω.
Rev. 0 | Page 5 of 36