12-Bit, 170 MSPS/210 MSPS/250 MSPS,
1.8 V Analog-to-Digital Converter
SNR = 64.8 dBFS @ fIN up to 70 MHz @ 250 MSPS
ENOB of 10.5 @ fIN up to 70 MHz @ 250 MSPS (−1.0 dBFS)
SFDR = 80 dBc @ fIN up to 70 MHz @ 250 MSPS (−1.0 dBFS)
DNL = ±0.3 LSB typical
INL = ±0.7 LSB typical
Single data port at up to 250 MHz
Interleaved dual port @ ½ sample rate up to 125 MHz
700 MHz full power analog bandwidth
On-chip reference, no external decoupling required
Integrated input buffer and track-and-hold
Low power dissipation
272 mW @ 170 MSPS
364 mW @ 250 MSPS
Programmable input voltage range
1.0 V to 1.5 V, 1.25 V nominal
1.8 V analog and digital supply operation
Selectable output data format (offset binary, twos
complement, Gray code)
Clock duty cycle stabilizer
Integrated data capture clock
The AD9626 is a 12-bit monolithic sampling analog-to-digital
converter optimized for high performance, low power, and ease
of use. The product operates at up to a 250 MSPS conversion
rate and is optimized for outstanding dynamic performance in
wideband carrier and broadband systems. All necessary func-
tions, including a track-and-hold (T/H) and voltage reference,
are included on the chip to provide a complete signal
The ADC requires a 1.8 V analog voltage supply and a differen-
tial clock for full performance operation. The digital outputs are
CMOS compatible and support either twos complement, offset
binary format, or Gray code. A data clock output is available for
proper output data timing.
Fabricated on an advanced CMOS process, the AD9626 is
available in a 56-lead LFCSP, specified over the industrial
temperature range (−40°C to +85°C).
Wireless and wired broadband communications
Cable reverse path
Communications test equipment
Radar and satellite subsystems
Power amplifier linearization
FUNCTIONAL BLOCK DIAGRAM
RESET SCLK SDIO CSB
Dx11 TO Dx0
1. High Performance—Maintains 64.9 dBFS SNR @ 250 MSPS
with a 70 MHz input.
2. Low Power—Consumes only 364 mW @ 250 MSPS.
3. Ease of Use—CMOS output data and output clock signal
allow interface to current FPGA technology. The on-chip
reference and sample-and-hold provide flexibility in
system design. Use of a single 1.8 V supply simplifies
system power supply design.
4. Serial Port Control—Standard serial port interface supports
various product functions, such as data formatting, clock
duty cycle stabilizer, power-down, gain adjust, and output
test pattern generation.
5. Pin-Compatible Family—10-bit pin-compatible family
offered as the AD9601.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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