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HA16163T
Synchronous Phase Shift Full-Bridge Control IC
Features
High frequency operation; oscillator frequency = 2 MHz max.
Full-bridge phase-shift switching circuit with adjustable delay times
Integrated secondary synchronous rectification control with adjustable delay times
www.DataSheet4U.cTohmree-level over current protection; pulse by pulse, timer Latch, one shot OCP
Package: TSSOP-20
Application
48 V input isolated DC/DC converter
Primary; Full-bridge circuit topology
Secondary; current doubler or center-tapped rectification
Illustrative Circuit
+48V
REJ03F0001-0600
Rev.6.00
Jul 01, 2008
+
Vbias
FET
Driver
FET
Driver
FET Driver
FET
Driver
FET
Driver
FET Driver
VCC OUT OUT
-A -B
CS RAMP OUT OUT
-C -D
OUT OUT
-E -F
Optical feedback circuitry
COMP
VREF
FB
GND
DELAY DELAY DELAY
RT SYNC SS REMOTE -1 -2 -3
REJ03F0001-0600 Rev.6.00 Jul 01, 2008
Page 1 of 29

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HA16163T
Pin Arrangement
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SYNC
RAMP
CS
COMP
REMOTE
FB
SS
DELAY-1
DELAY-2
DELAY-3
1 20
2 19
3 18
4 17
5 16
6 15
7 14
8 13
9 12
10 11
(Top view)
RT
GND
OUT-A
OUT-B
OUT-C
OUT-D
OUT-E
OUT-F
VCC
VREF
Pin Functions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin Name
SYNC
RAMP
CS
COMP
REMOTE
FB
SS
DELAY-1
DELAY-2
DELAY-3
VREF
VCC
OUT-F
OUT-E
OUT-D
OUT-C
OUT-B
OUT-A
GND
RT
Pin Function
Synchronization I/O for the oscillator
Current sense signal input for the full-bridge control loop
Current sense signal input for OCP
Error amplifier output
Remote on/off control
Voltage feedback input
Timing capacitor for both soft start and timer latch
Delay time adjustor for the full-bridge control signal (OUT-A and B)
Delay time adjustor for the full-bridge control signal (OUT-C and D)
Delay time adjustor for the secondary control signal (OUT-E and F)
5 V/20 mA Output
IC power supply input
Secondary control signal
Secondary control signal
Full-bridge control signal
Full-bridge control signal
Full-bridge control signal
Full-bridge control signal
Ground level for the IC
Timing resistor for the oscillator
REJ03F0001-0600 Rev.6.00 Jul 01, 2008
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HA16163T
Block Diagram
VCC
REMOTE
RT
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SYNC
FB
COMP
RAMP
SS
CS
H UVL
UVLO
L
ON: 1.417V
OFF: 1.333V
+
VREF
Current Ref.
Generator
5V
Generator
VREF H
GOODL
Start-up
counter
32 clock
VREFGOOD
DELAY
SYNC. I/O
Oscillator
RES
Q
Error Amp
VREF
500μ
+
1.25V
20k
10k
Comparator
+
0.4V
R
Q
S
1.55V
1.46V
+
DELAY
DELAY
DELAY
Clamp Circuit
VREF
87μA
4V RES
10μ
R
Q
S
R
Q
S
VREFGOOD
SS IN
LOCKOUT
SEQ.
ONE PULSE
DISCHARGE
Zero Delay
DELAY
+
0.4V
+
0.6V
PULSE BY PULSE
ONE SHOT
FAULT
LOGIC
LIMIT IN
Zero delay
DELAY
GND
Note that all switches in the block diagram are turned on when control signal is high.
VREF
Circuit Bias
VREF
OUT-A
VREF
VREF
DELAY-1
OUT-B
OUT-C
VREF
DELAY-2
OUT-D
VREF
OUT-E
VREF
DELAY-3
OUT-F
REJ03F0001-0600 Rev.6.00 Jul 01, 2008
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HA16163T
Absolute Maximum Ratings
Item
Symbol
Rating
Unit
Power supply voltage
Vcc
20 V
Peak output current
Ipk-out
±50 mA
DC output current
Idc-out
±5 mA
VREF output current
Iref-out
–20 mA
COMP sink current
Isink-comp
2 mA
DELAY set current
Iset-delay
0.3 mA
RT set current
Iset-rt
0.3 mA
VREF terminal voltage
Vter-ref
–0.3 to 6
V
Terminal group 1 voltage
Vter-1
–0.3 to (Vref +0.3)
V
www.DataSheetO4Up.ecroamting junction temperature
Tj-opr
–40 to +125
°C
Storage temperature
Tstg
–55 to +150
°C
Notes: 1. Rated voltages are with reference to the GND pin.
2. Shows the transient current when driving a capacitive load.
3. For rated currents, inflow to the IC is indicated by (+), and outflow by (–).
4. VREF pin voltage must not exceed VCC pin voltage.
5. Terminal group 1 is defined the pins;
REMOTE, CS, RAMP, COMP, FB, SS, RT, SYNC, DELAY-1 to 3, OUT-A to F
6. θja
228°C/W Board condition; Glass epoxy 55 mm × 45 mm × 1.6 mm, 10% wiring density.
(Ta = 25°C)
Note
1
2, 3
3
3
3
3
3
1, 4
1, 5
6
REJ03F0001-0600 Rev.6.00 Jul 01, 2008
Page 4 of 29

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HA16163T
Electrical Characteristics
(Ta = 25°C, Vcc = 12 V, RT = 33 kΩ, Rdelay = 51 kΩ, unless otherwise specified.)
Item
Symbol Min Typ Max Unit
Test Conditions
Supply
Start threshold
VH
9.0 9.8 10.6
V
Shutdown threshold
VL
7.3 7.9 8.5
V
UVLO hysteresis
Start-up current
dVUVL
Is
1.7 1.9 2.1
V
— 90 150 μA Vcc = 8.5V
Operating current
Icc
— 7 10 mA No load on VREF pin
VREF
Output voltage
Vref
4.9 5.0 5.1
V
Line regulation
Vref-line — 0 10 mV Vcc = 10V to 16V
Oscillator
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Load regulation
Temperature stability
Oscillator frequency
Switching frequency
Vref-load
dVref/dTa
fosc
fsw
— 6 20 mV Iref = –1mA to –20mA
— ±80 *1 — ppm/°C Ta = –40 to 105°C
— 960 *1
kHz
412 480 547
kHz Measured on OUT-A, -B
Line stability
Temperature stability
fsw-line
dfsw/dTa
–1.5
0
±0.1 *1
1.5
%
%/°C
Vcc = 10V to 16V
Ta = –40 to 105°C
RT voltage
VRT
2.5 2.7 2.9
V
SYNC
Input threshold
Output high
Output low
VTH-SYNC
VOH-SYNC
VOL-SYNC
2.5 2.85 3.2
3.5 4.0 —
— 0.05 0.15
V
V RSYNC = 33kΩ to GND
V RSYNC = 33kΩ to VREF
Minimum input pulse
TI-MIN
50 — —
ns
Output pulse width
TO-SYNC
— 500 —
ns
Remote
On threshold voltage
VON
1.374
1.417
1.460
V
Off threshold voltage
VOFF
1.293
1.333
1.373
V
Input bias current
IREMOTE
0 0.4 2
μA REMOTE = 2V
Error
amplifier
FB input voltage
FB input current
Open-loop DC gain
Unity gain bandwidth
VFB
IFB
Av
BW
1.225
–1.0
1.250
0
80 *1
2 *1
1.275
1.0
V
μA
dB
MHz
FB and COMP are shorted
FB = 1.25V
Output source current
ISOURCE
–610
–430
–350
μA FB = 0.75V, COMP = 2V
Output sink current
ISINK
2.0 6.5 — mA FB = 1.75V, COMP = 2V
Output high voltage
VOH-EO
3.7 3.9 —
V FB = 0.75V, COMP; open
Output low voltage
Output clamp voltage *2
VOL-EO
VCLAMP-EO
–0.16
0.1
–0.07
0.4
0.0
V FB = 1.75V, COMP; open
V FB = 0.75V, COMP; open
SS = 1V
Notes: 1. Reference values for design. Not 100% tested in production.
2. VCLAMP-EO = VCOMP – SS voltage (1V)
REJ03F0001-0600 Rev.6.00 Jul 01, 2008
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