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Ordering number : ENA0599
www.DataSheet4U.com
LA6560
Monolithic Linear IC
For CD
Five-Channel Driver
(BTL : Four-Channel, H Bridge : One-Channel)
Overview
The LA6560 is a 5-channel driver (BTL : 4-channel, H bridge : 1-channel) for CD players.
Functions
Power amplifier 5-channel built-in. (Bridge-connection (BTL) : 4-channel, H bridge : 1-channel)
IO max 1A
Level shift circuit built-in (except H bridge).
Mute circuit (output ON/OFF) built-in.
(Operable with BTL AMP and not operable for the H bridge of 5VREG)
5V regulator built-in (external PNP transistor).
With VREF changeover function (H : external, L : internal (2.5V) selected)
Overheat protection circuit (thermal shutdown) built-in.
Specifications
Maximum Ratings at Ta = 25°C
Parameter
Supply voltage
Allowable power dissipation
Symbol
VCC max
Pd max
Maximum output current
Maximum input voltage
MUTE pin voltage
IO max
VINB
VMUTE
Operating temperature
Topr
Storage temperature
Tstg
* Specified board size : 76.1×114.3×1.6mm3, glass epoxy.
Conditions
Independent IC
Mounted on specified board. *
Each output for H bridge, channel 1 to 4.
Recommended Operating Conditions at Ta = 25°C
Parameter
Supply voltage
Symbol
VCC
Conditions
Ratings
14
2.0
0.8
1
13
13
-30 to +85
-55 to +150
Unit
V
W
W
A
V
V
°C
°C
Ratings
5.6 to 13
Unit
V
Any and all SANYO Semiconductor products described or contained herein do not have specifications
that can handle applications that require extremely high levels of reliability, such as life-support systems,
aircraft's control systems, or other applications whose failure can be reasonably expected to result in
serious physical and/or material damage. Consult with your SANYO Semiconductor representative
nearest you before using any SANYO Semiconductor products described or contained herein in such
applications.
SANYO Semiconductor assumes no responsibility for equipment failures that result from using products
at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor
products described or contained herein.
D0606 MS PC B8-6307 No.A0599-1/9

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LA6560
Electrical Characteristics at Ta = 25°C, VCC1 = VCC2 = 8V, VREF = 2.5V, unless especially specified.
Parameter
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Symbol
Conditions
Ratings
min typ max
Unit
ALL Blocks
No-load current drain ON
No-load current drain OFF
Thermal shutdown temperature
ICC-ON
ICC-OFF
TSD
BTL-AMP output ON,
LOADING block OFF *1
All outputs OFF *1
Design guarantee value
30 50 mA
10 15 mA
150 175 200 °C
VREF AMP
VREF-AMP offset voltage
VREF-OFFSET
-10 10 mV
VREF Input voltage range
VREF-OUT output current
VREF-IN
I-VREF-OUT
CH1 input reference voltage
1
VCC-1.5
V
2 5 6.6 mA
BTL AMP Block (CH1 to CH4)
Output offset voltage
Input voltage range
Output voltage
Closed-circuit voltage gain
Slew rate
MUTE ON voltage
VOFF
Voltage difference between outputs for BTL
AMP, each channel. *2
-50
50 mV
VIN Input voltage range for input for OP-AMP.
0
VCC-1.5
mA
VO Each voltage between V0+ and V0- when
RL = 8Ω. *3
5.7 6.2
V
VG Input and output gain.
3.6 4 4.4 Times
Input OP-AMP:BUFFER
SR AMP Independent
0.5 V/μs
Multiply 2 between outputs.
VMUTE-ON
Output ON voltage, each MUTE *4
2
V
MUTE OFF voltage
VMUTE-OFF Output OFF voltage, each MUTE *4
0.5 V
Input AMP Block (CH1 to 4)
Input voltage range
Output current (SINK)
VIN-OP
SINK-OP
0
VCC-1.5
V
2 mA
Output current (SOURCE)
SOURCE-OP *5
300 500
μA
Output offset voltage
CH1 input changeover voltage 1
VOFF-OP
VSW-OP1
CH1 input AMP(B), external REF select *6
-10
2
10 mV
V
CH1 input changeover voltage 2
VSW-OP2
CH1 input AMP(A), internal VREF select *6
0.5 V
Loading Block (CH5, H bridge)
Output voltage
VO-LOAD
Break output saturation voltage
VCE-BREAK
Input low level
VIN-L
Input high level
VIN-H
Power Supply Block (PNP transistor : 2SB632K-use)
At forward and reverse rotation,
RL = 8Ω, VCONT=VCC *3
Output voltage at braking *7
5.7 6.5
V
0.3 V
1V
2V
5V supply voltage
REG-IN SINK current
VOUT
REG-IN-SINK
IO = 200mA
Base current of external PNP *8
4.8 5.0 5.2 V
5 10
mA
Line regulation
Load regulation
ΔVOLN
ΔVOLD
6V VCC 12V, IO = 200mA
5mA IO 200mA
10 100 mV
10 100 mV
Note *1 : Current dissipation that is a sum of VCC1 and VCC2 at no load.
*2 : Input AMP is a BUFFER AMP.
*3 : Voltage difference between both ends of load (8Ω). Output saturated.
*4 : Output ON with MUTE : [H] and OFF with MUTE : [L] (HI impedance).
*5 : The source of input OP-AMP is a constant current. As the 11kΩ resistance to the next stage is a load, pay due attention when setting the input
OP-AMP gain.
*6 : With VIN1-SW : [L], the input AMP selects AMP-A while VREF selects internal VREF (2.5V).
With VIN1-SW : [H], the input AMP selects AMP-B while VREF selects external VREF (VREF-IN).
*7 : Short (GND) brake used. SINK side output ON.
*8 : 5VREG incorporates a drooping protection circuit and operated when the base current is 10mA (TYP).
No.A0599-2/9

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Package Dimensions
unit : mm (typ)
w32w5w1.DataSheet4U.com
17.8
(6.2)
36 19
LA6560
(0.5) 1
0.8 2.0
18
0.3
0.25
2.7
SANYO : HSOP36R(375mil)
Pd max -- Ta
2.5
Specified board : 76.1×114.3×1.6mm3
glass epoxy
When mounted on a board
2
1.5
1
Independent IC
0.8
0.5
1.04
0.42
0
--30 --20
0 20 40 60 80
Ambient temperature, Ta – °C
100
No.A0599-3/9

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Block Diagram
LA6560
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FWD 1
REV 2
VCC2 3
VLO- 4
VLO+ 5
VO4+ 6
Thermal shutdown
Signal system GND
36 S-GND
(LOAD output voltage setting)
35 VCONT
BTL-AMP Output
ON/OFF MUTE
34 MUTE
22kΩ
11kΩ
33 VIN4
32 VIN4-
31 VIN4+
VO4- 7
30 VREF-IN
VO3+ 8
VIN1/VREF-SW
29 VIN1(VREF)-SW
VO3- 9
Power system GND
FR FR
28 VREF-OUT(CH1)
Power system GND
FR FR
5VREG (Extemal PNP)
VO2+ 10
27 REG-OUT
VO2- 11
VO1+ 12
VO1- 13
22kΩ
11kΩ
26 REG-IN
25 VIN3+
24 VIN3-
VCC1 14
VIN1 15
VIN1-A 16
VIN1+A 17
VIN1-B 18
22kΩ
11kΩ
22kΩ
11kΩ
AMP-A
AMP-B
[L] [H]
VIN1 (VREF)-SW
[L]:Internal VREF (2.5V fixed)
[H]:Internal VREF
VIN1 (VREF)-SW
[L]:AMP-A
[H]:AMP-B
23 VIN3
22 VIN2+
21 VIN2-
20 VIN2
19 VIN1+B
No.A0599-4/9

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LA6560
Pin Functions
Pin No.
Symbol
Pin descriptions
www.D1ataSheet4U.comFWD
Output change pin (FWD) for 5CH (VLO), logic input for loading block.
2
REV
Output change pin (REV) for 5CH (VLO), logic input for loading block.
3
VCC2
Power supply for CH3, 4, and 5.
4
VLO-
Loading output (-)
5
VLO+
Loading output (+)
6
VO4+
Output pin (+) for channel 4
7
VO4-
Output pin (-) for channel 4
8
VO3+
Output pin (+) for channel 3
9
VO3-
Output pin (-) for channel 3
10
VO2+
Output pin (+) for channel 2
11
VO2-
Output pin (-) for channel 2
12
VO1+
Output pin (+) for channel 1
13
VO1-
Output pin (-) for channel 1
14
VCC1
Power supply for CH1, 2 (BTL).
15
VIN1
Input pin for channel 1
16
VIN1-A
OP-AMP input AMP-A input pin (-)
17
VIN1+A
OP-AMP input AMP-A input pin (+)
18
VIN1-B
Input AMP-B input pin (-) for channel 1
19
VIN1+B
Input AMP-B input pin (+) for channel 1
20
VIN2
Input pin for channel 2, input AMP output
21
VIN2-
Input pin (-) for channel 2
22
VIN2+
Input pin (+) for channel 2
23
VIN3
Input pin for channel 3, input AMP output
24
VIN3-
Input pin (-) for channel 3
25
VIN3+
Input pin (+) for channel 3
26
REG-IN
PNP transistor base connected
27
REG-OUT
5V power output to which the PNP transistor collector connected.
28
VREF-OUT
CH1 reference voltage output. Outputs internal VREF (2.5V : TYP) or external VREF.
29 VIN1 (VREF) -SW Pin for changeover between input AMP-A/internal VREF (TYP2.5V) and input AMP-B/ external VREF.
30
VREF-IN
Reference voltage applied pin
31
VIN4+
Input pin (+) for channel 4
32
VIN4-
Input pin (-) for channel 4
33
VIN4
Input pin for channel 4, input AMP output
34
MUTE
All BTL AMP output ON/OFF
35
VCONT
LOADING output voltage setting
36
S-GND
Signal system GND
Note : Center frame (FR) becomes GND for the power system (P-GND). Set this to the minimum potential together with S-GND.
No.A0599-5/9