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DS1852
Optical Transceiver Diagnostic Monitor
www.maxim-ic.com
FEATURES
§ Implements proposals of SFF-8472 at device address A2h
[Note: requires use of external EEPROM at address
A0h for full compliance.]
§ Scaleable four-input muxing analog-to-digital converter (ADC)
Top View
§ Direct-to-digital temperature converter
A
§ Programmable alarm and warning conditions
§ Temperature-compensated, programmable three-input muxing
B
fast comparator
§ Access temperature, data, and device control through a 2-wire
C
interface
D
§ Operates from 3V or 5V supplies
§ Packaging: 25-ball BGA
E
§ Operating temperature: -40°C to +100°C
§ Programming temperature: 0°C to +70°C
§ Three levels of security
§ 127 bytes EEPROM for security level 1
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5 x 5 BGA (0.8mm pitch)
§ 128 bytes EEPROM for security level 2
§ Address space is GBIC compliant (with use of external EEPROM at device address A0h)
ORDERING INFORMATION
DS1852B-000
25-BALL BGA
DESCRIPTION
The DS1852 transceiver monitor manages all system monitoring functions in a fiber optic data
transceiver module, in accordance with proposal SFF-8472. Its functions include 2-wire communications
with the host system, EEPROM memory for identification, tracking, and calibration, an ADC with four
muxing inputs, three fast comparators, and a temperature sensor to monitor an optical transceiver. The
DS1852 has programmable alarm and warning flags for all four analog-to-digital (A/D) conversion
values (three user analog inputs plus supply voltage) as well as the temperature. These conditions can be
used to determine critical parameters inside each module. The three fast comparators have temperature-
compensated programmability. The temperature dependencies of the trip points aid in assessing critical
conditions.
The DS1852 is offered for sale free of any royalty or licensing fees. However, users should be aware that implementation of the SFF-8472
proposed specifications may require the use of an invention covered by patent rights. Since these patents relate to the SFF-8472 specification
and not to the DS1852 itself, licensing questions should be directed to Finisar Corp.
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061302

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DS1852
PIN DESCRIPTIONS
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Name Ball Locations
VCC D2, D4, E3
GND B3, C2, C4, D3
SDA B5
SCL A5
Bin A3
Pin D1
Rin A2
ASEL B2
Din C5
RSin B4
Fin E5
Lin A1
NC A4, B1, C1, D5,
E1, E2, E4, C3
Description
Power-Supply Terminal. The DS1852 will support supply voltages
ranging from +2.7V to +5.5V.
Ground Terminal
2-Wire Serial Data. The serial data pin is for serial data transfer to and
from the DS1852. The pin is open drain and may be wire-OR’ed with
other open-drain or open-collector interfaces.
2-Wire Serial Clock. The serial clock input is used to clock data into
the DS1852 on rising edges and clock data out on falling edges.
Analog Input Pin (Bias Value). Input to A/D.
Analog Input Pin (Power Level). Input to A/D.
Analog Input Pin (Received Power). Input to A/D.
Address Select Pin. If set to logic 0, the device address is A0h. If set to
logic 1, the value in Table 3, byte D0h determines the chip address
(factory default is A2h). For SFF-8472 compliance, this pin should be
connected high.
Digital Input Pin (TX Disable). Digital input for mirroring in memory
map.
Digital Input Pin (Rate Select). Digital input for mirroring in memory
map.
Digital Input Pin (TX Fault). Digital input for mirroring in memory
map.
Digital Input Pin (LOS). Digital input for mirroring in memory map.
No Connect
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DS1852 BLOCK DIAGRAM Figure 1
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VCC
DS1852
BIN
PIN
RIN
SDA
SCL
TEMP
SENSOR
Control
2-WIRE
Interface
OUTPUT REGISTERS
5:1
MUX
ADC
Control
3:1
MUX
Control
FAST
TRIP
Control
Control
T
V
B
P
R
FAST
ALARM
WARN
ALARM
and
WARN
EEPROM
CUSTOMER CONTROL
EEPROM SETTINGS
CONTROL
LOGIC
Control
Signals
Control
GND
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DS1852
DEVICE OPERATION
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Security
To prevent accidental overwrites of key device data, a data lockout feature is incorporated. A 32-bit
password provides access to the “manufacturer” memory locations. These locations are in addition to the
unprotected “user” memory locations:
1) User—This is the default state after power-up; it allows read access to standard IEEE identity table
and standard monitoring and status functions.
2) Manufacturer Level 1—This allows access to customer data table and some selected setups (password
1).
3) Manufacturer Level 2—This allows access to all memory, settings, and features (password 2).
The level 1 password is located in Table 03h EEPROM (bytes D3h to D6h) and may be changed by
gaining access through the level 2 password.
The level 2 password is set in protected EEPROM and is programmed during factory test.
During power-up, the 32-bit password entry (addresses 7Bh to 7Eh) is set to all 1s. This is the value that
is compared to the level 1 password entry in Table 03h to grant level 1 access. Therefore, the level 1
password should not be set to all 1s or the user will gain level 1 access after each power-on.
By default, both passwords are factory preset to 00h.
To gain access to a security level, a 4-byte password is written into Table 00h, bytes 7Bh to 7Eh. If the
written data matches one of the passwords, that corresponding level of access is granted until the
password entry is changed or the power is cycled. Entering the level 2 password allows access to both
the level 1 data and the level 2 data. The 4-byte password is write-only.
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DS1852
ANALOG-TO-DIGITAL CONVERTER
TwhwewA.DDatCaShreeeat4dUs.caomtotal of five inputs: VCC (internal), temperature (internal), and external inputs Bin, Pin,
and Rin. All conversions are updated every 13ms (nominal) or 20ms (max) in rotation. The conversions
are absolute and compared to an internal reference. While the 16-bit values are read, only the upper 12
are significant. The lower four bits are undefined.
The temperature and analog voltage inputs are calibrated by Dallas Semiconductor and read with the
following scale:
Temperature: High byte: -128°C to +127°C signed; low byte: 1/256°C. The lower four bits
should be ignored.
S 26 25 24 23 22 21 20
2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8
VCC: This reads as an unsigned 16-bit quantity at 100mV LSB, with a maximum range of
6.5535V, when using the factory default value. The lower four bits should be ignored.
Bin, Pin, Rin: These read as an unsigned 16-bit quantity at 38.147mV LSB, with a maximum range
of 2.500V, when using factory default values. The lower four bits should be ignored.
215 214 213 212 211 210 29
27 26 25 24 23 22 21
28
20
Each analog input has a 16-bit scaling calibration in Table 03h EEPROM. This allows the analog
conversion values to be calibrated for full scale at any input voltage from 0.2V to 6.5535V. The ADC
conversion value will clamp rather than roll over. Each external analog channel has a maximum input
voltage of VCC independent of the calibration factor.
The upper four bits of scaling select the coarse range; the lower 12 bits are for fine adjustments. The
algorithm to trim the scale is described below.
The scaling factors for each input (VCC, VBin, VPin, and VRin) are 16 bits wide. They are located in
Table 03h at addresses C8h to CFh, respectively. The 16 bits are a combination of two trims. The lower
12 bits are binary weighted and give the high resolution trim for scaling the input to output relationship.
The upper four bits are a coarse-adjust of the lower 12 bits. In other words, the upper four bits scale the
LSB value of the binary weighted lower 12 bits.
As an illustration, assume a value of 1V is needed to read full scale. Force a voltage less than 1V
(975mV, for example) to keep clamping out of the way. The closer to max voltage the better, but not too
close.
1) Set the scale trim to 0FFFh (the upper four bits to all zeros and the lower 12 bits to all ones).
2) Use a SAR approach on the upper four bits, starting with 1000b, to find the smallest 4-bit trim
necessary to cause the voltage reading to be above the input (in this case, greater than or equal to
975mV). If they all clamp, that is okay. That means 0000b is the needed value for the upper four
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