LTC2262-14.pdf 데이터시트 (총 28 페이지) - 파일 다운로드 LTC2262-14 데이타시트 다운로드

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FEATURES
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n 72.8dB SNR
n 88dB SFDR
n Low Power: 149mW
n Single 1.8V Supply
n CMOS, DDR CMOS or DDR LVDS Outputs
n Selectable Input Ranges: 1VP-P to 2VP-P
n 800MHz Full-Power Bandwidth S/H
n Optional Data Output Randomizer
n Optional Clock Duty Cycle Stabilizer
n Shutdown and Nap Modes
n Serial SPI Port for Configuration
n Pin Compatible 14-Bit and 12-Bit Versions
n 40-Pin (6mm × 6mm) QFN Package
APPLICATIONS
n Communications
n Cellular Base Stations
n Software Defined Radios
n Portable Medical Imaging
n Multi-Channel Data Acquisition
n Nondestructive Testing
Electrical Specifications Subject to Change
LTC2262-14
14-Bit, 150Msps
Ultralow Power 1.8V ADC
DESCRIPTION
The LTC®2262-14 is a sampling 14-bit A/D converter de-
signed for digitizing high frequency, wide dynamic range
signals. The LTC2262-14 is perfect for demanding commu-
nications applications with AC performance that includes
72.8dB SNR and 88dB spurious free dynamic range (SFDR).
Ultralow jitter of 0.17psRMS allows undersampling of IF
frequencies with excellent noise performance.
DC specs include ±1LSB INL (typical), ±0.3LSB DNL (typi-
cal) and no missing codes over temperature. The transition
noise is a low 1.2LSBRMS.
The digital outputs can be either full rate CMOS, double
data rate CMOS, or double data rate LVDS. A separate
output power supply allows the CMOS output swing to
range from 1.2V to 1.8V.
The ENC+ and ENCinputs may be driven differentially
or single ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
ANALOG
INPUT
+
INPUT
S/H
150MHz
CLOCK
CLOCK/DUTY
CYCLE
CONTROL
1.8V
VDD
14-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
OUTPUT
DRIVERS
1.2V
TO 1.8V
OVDD
D13
• CMOS
• OR
• LVDS
D0
OGND
GND
226214 TA01a
2-Tone FFT, fIN = 68MHz and 69MHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
10 20 30 40 50 60 70
FREQUENCY (MHz)
226214 TA01b
226214p
1

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LTC2262-14
ABSOLUTE MAXIMUM RATINGS (Notes 1, 2)
Supply Voltages (VDD, OVDD)....................... –0.3V to 2V
Analog Input Voltage (AIN+, AIN–,
wwwP.dAatRas/SheEeRt4,uS.cEomNSE) (Note 3)...........–0.3V to (VDD + 0.2V)
Digital Input Voltage (ENC+, ENC, CS,
SDI, SCK) (Note 4).................................... –0.3V to 3.9V
SDO (Note 4) ............................................ –0.3V to 3.9V
Digital Output Voltage ................ –0.3V to (OVDD + 0.3V)
Operating Temperature Range:
LTC2262C ................................................ 0°C to 70°C
LTC2262I.............................................. –40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
PIN CONFIGURATIONS
FULL-RATE CMOS OUTPUT MODE
TOP VIEW
DOUBLE DATA RATE CMOS OUTPUT MODE
TOP VIEW
AIN+ 1
AIN– 2
GND 3
REFH 4
40 39 38 37 36 35 34 33 32 31
30 D9
29 D8
28 CLKOUT+
27 CLKOUT
REFH 5
REFL 6
41 26 OVDD
25 OGND
REFL 7
PAR/SER 8
24 D7
23 D6
VDD 9
22 D5
VDD 10
21 D4
11 12 13 14 15 16 17 18 19 20
AIN+ 1
AIN– 2
GND 3
REFH 4
40 39 38 37 36 35 34 33 32 31
30 D8_9
29 DNC
28 CLKOUT+
27 CLKOUT
REFH 5
REFL 6
41 26 OVDD
25 OGND
REFL 7
PAR/SER 8
24 D6_7
23 DNC
VDD 9
22 D4_5
VDD 10
21 DNC
11 12 13 14 15 16 17 18 19 20
UJ PACKAGE
40-LEAD (6mm s 6mm) PLASTIC QFN
TJMAX = 150°C, θJA = 32°C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
UJ PACKAGE
40-LEAD (6mm s 6mm) PLASTIC QFN
TJMAX = 150°C, θJA = 32°C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
DOUBLE DATA RATE LVDS OUTPUT MODE
TOP VIEW
2
AIN+ 1
AIN– 2
GND 3
REFH 4
40 39 38 37 36 35 34 33 32 31
30 D8_9+
29 D8_9
28 CLKOUT+
27 CLKOUT
REFH 5
REFL 6
41 26 OVDD
25 OGND
REFL 7
24 D6_7+
PAR/SER 8
23 D6_7
VDD 9
VDD 10
22 D4_5+
21 D4_5
11 12 13 14 15 16 17 18 19 20
UJ PACKAGE
40-LEAD (6mm s 6mm) PLASTIC QFN
TJMAX = 150°C, θJA = 32°C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
226214p

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LTC2262-14
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2262CUJ-14#PBF LTC2262CUJ-14#TRPBF LTC2262UJ-14
40-Lead (6mm × 6mm) Plastic QFN
0°C to 70°C
wwwL.dTCat2a2s6h2eIUetJ4-u1.4c#oPmBF
LTC2262IUJ-14#TRPBF
LTC2262UJ-14
40-Lead (6mm × 6mm) Plastic QFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
Resolution (No Missing Codes)
l 14
Bits
Integral Linearity Error
Differential Analog Input (Note 6)
l –3.75 ±1 3.75
LSB
Differential Linearity Error
Differential Analog Input
l –0.9 ±0.3 0.9
LSB
Offset Error
(Note 7)
l –9 ±1.5 9
mV
Gain Error
Internal Reference
External Reference
±1.5
l –1.5 ±0.4 1.5
%FS
%FS
Offset Drift
±20 μV/°C
Full-Scale Drift
Internal Reference
External Reference
±30 ppm/°C
±10 ppm/°C
Transition Noise
External Reference
1.2 LSBRMS
ANALOG INPUT The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
VIN
VIN(CM)
VSENSE
IINCM
IIN1
IIN2
IIN3
tAP
Analog Input Range (AIN+ – AIN–)
1.7V < VDD < 1.9V
l
Analog Input Common Mode (AIN+ + AIN–)/2 Differential Analog Input (Note 8) l VCM – 100mV
External Voltage Reference Applied to SENSE External Reference Mode
l 0.625
Analog Input Common Mode Current
Analog Input Leakage Current
PAR/SER Input Leakage Current
SENSE Input Leakage Current
Per Pin, 150Msps
0 < AIN+, AIN– < VDD, No Encode
0 < PAR/SER < VDD
0.625 < SENSE < 1.3V
l
l
l
–1
–3
–6
Sample-and-Hold Acquisition Delay Time
1 to 2
VCM
1.250
185
0
VCM + 100mV
1.300
1
3
6
VP-P
V
V
μA
μA
μA
μA
ns
tJITTER
CMRR
Sample-and-Hold Acquisition Delay Jitter
Analog Input Common Mode Rejection Ratio
0.17 psRMS
80 dB
BW-3B Full-Power Bandwidth
Figure 6 Test Circuit
800 MHz
226214p
3

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LTC2262-14
DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
SNR Signal-to-Noise Ratio
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5MHz Input
30MHz Input
70MHz Input
140MHz Input
l
72.8
72.7
72.5
72.1
dB
dB
dB
dB
SFDR
Spurious Free Dynamic Range
2nd or 3rd Harmonic
5MHz Input
30MHz Input
70MHz Input
140MHz Input
l
88
88
82
81
dB
dB
dB
dB
Spurious Free Dynamic Range
4th Harmonic or Higher
5MHz Input
30MHz Input
70MHz Input
140MHz Input
l
90
90
90
90
dB
dB
dB
dB
S/(N+D)
Signal-to-Noise Plus Distortion Ratio
5MHz Input
30MHz Input
70MHz Input
140MHz Input
l
72.7
72.5
72
71.6
dB
dB
dB
dB
INTERNAL REFERENCE CHARACTERISTICS The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
VCM Output Voltage
VCM Output Temperature Drift
VCM Output Resistance
VREF Output Voltage
VREF Output Temperature Drift
VREF Output Resistance
IOUT = 0
–600μA < IOUT < 1mA
IOUT = 0
–400μA < IOUT < 1mA
0.5 • VDD – 25mV
1.225
0.5 • VDD
±25
4
1.250
±25
7
0.5 • VDD + 25mV
1.275
V
ppm/°C
Ω
V
ppm/°C
Ω
VREF Line Regulation
1.7V < VDD < 1.9V
0.6 mV/V
DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
ENCODE INPUTS (ENC+, ENC)
Differential Encode Mode (ENCNot Tied to GND)
CONDITIONS
MIN TYP MAX UNITS
VID Differential Input Voltage
VICM Common Mode Input Voltage
VIN Input Voltage Range
RIN Input Resistance
CIN Input Capacitance
Single-Ended Encode Mode (ENCTied to GND)
(Note 8)
Internally Set
Externally Set (Note 8)
ENC+, ENCto GND
(See Figure 10)
(Note 8)
l 0.2
V
1.2
l 1.1
1.6
V
V
l 0.2
3.6 V
10 kΩ
3.5 pF
VIH High Level Input Voltage
VIL Low Level Input Voltage
VIN Input Voltage Range
RIN Input Resistance
CIN Input Capacitance
VDD = 1.8V
VDD = 1.8V
ENC+ to GND
(See Figure 11)
(Note 8)
l 1.2
V
l 0.6 V
l0
3.6 V
30 kΩ
3.5 pF
226214p
4

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LTC2262-14
DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
DIGITAL INPUTS (CS, SDI, SCK)
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VIH High Level Input Voltage
VDD = 1.8V
VIL Low Level Input Voltage
VDD = 1.8V
IIN Input Current
VIN = 0V to 3.6V
CIN Input Capacitance
(Note 8)
SDO OUTPUT (Open-Drain Output. Requires 2k Pull-Up Resistor if SDO is Used)
MIN TYP MAX UNITS
l 1.3
V
l 0.6 V
l –10
10 μA
3 pF
ROL Logic Low Output Resistance to GND VDD = 1.8V, SDO = 0V
IOH Logic High Output Leakage Current
SDO = 0V to 3.6V
COUT Output Capacitance
(Note 8)
DIGITAL DATA OUTPUTS (CMOS MODES: FULL DATA RATE AND DOUBLE DATA RATE)
200 Ω
l –10
10 μA
4 pF
OVDD = 1.8V
VOH High Level Output Voltage
VOL Low Level Output Voltage
OVDD = 1.5V
VOH High Level Output Voltage
VOL Low Level Output Voltage
OVDD = 1.2V
VOH High Level Output Voltage
VOL Low Level Output Voltage
DIGITAL DATA OUTPUTS (LVDS MODE)
VOD Differential Output Voltage
VOS Common Mode Output Voltage
RTERM On-Chip Termination Resistance
IO = –500μA
IO = 500μA
IO = –500μA
IO = 500μA
IO = –500μA
IO = 500μA
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
Termination Enabled, OVDD = 1.8V
l 1.750
l
l 247
l 1.125
1.790
0.010
1.488
0.010
1.185
0.010
350
175
1.250
1.250
100
0.050
454
1.375
V
V
V
V
V
V
mV
mV
V
V
Ω
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
CMOS Output Modes: Full Data Rate and Double Data Rate
VDD
OVDD
IVDD
Analog Supply Voltage
Output Supply Voltage
Analog Supply Current
(Note 10)
(Note 10)
DC Input
Sine Wave Input
l 1.7
l 1.1
l
1.8 1.9
1.9
82.7
84.5
V
V
mA
mA
IOVDD
PDISS
Digital Supply Current
Power Dissipation
Sine Wave Input, OVDD=1.2V
DC Input
Sine Wave Input, OVDD=1.2V
l
5.5
149
159
mA
mW
mW
226214p
5