LTC2283.pdf 데이터시트 (총 24 페이지) - 파일 다운로드 LTC2283 데이타시트 다운로드

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FEATURES
www.datasheet4u.com
n Integrated Dual 12-Bit ADCs
n Sample Rate: 125Msps
n Single 3V Supply (2.85V to 3.4V)
n Low Power: 790mW
n 70.2dB SNR, 88dB SFDR
n 110dB Channel Isolation at 100MHz
n Flexible Input: 1VP-P to 2VP-P Range
n 640MHz Full Power Bandwidth S/H
n Clock Duty Cycle Stabilizer
n Shutdown and Nap Modes
n Data Ready Output Clock
n Pin Compatible Family
125Msps: LTC2283 (12-Bit), LTC2285 (14-Bit)
105Msps: LTC2282 (12-Bit), LTC2284 (14-Bit)
80Msps: LTC2294 (12-Bit), LTC2299 (14-Bit)
65Msps: LTC2293 (12-Bit), LTC2298 (14-Bit)
40Msps: LTC2292 (12-Bit), LTC2297 (14-Bit)
n 64-Pin (9mm × 9mm) QFN Package
APPLICATIONS
n Wireless and Wired Broadband Communication
n Imaging Systems
n Spectral Analysis
n Portable Instrumentation
LTC2283
Dual 12-Bit, 125Msps
Low Power 3V ADC
DESCRIPTION
The LTC®2283 is a 12-bit 125Msps, low power dual 3V
A/D converter designed for digitizing high frequency,
wide dynamic range signals. The LTC2283 is perfect for
demanding imaging and communications applications
with AC performance that includes 70.1dB SNR and 82dB
SFDR for signals at the Nyquist frequency.
Typical DC specs include ±0.4LSB INL, ±0.2LSB DNL. The
transition noise is a low 0.32LSBRMS.
A single 3V supply allows low power operation. A separate
output supply allows the outputs to drive 0.5V to 3.6V
logic.
A single-ended CLK input controls converter operation.
An optional clock duty cycle stabilizer allows high perfor-
mance at full speed for a wide range of clock duty cycles.
A data ready output clock (CLKOUT) can be used to latch
the output data.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
TYPICAL APPLICATION
ANALOG
INPUT A
+
INPUT
S/H
12-BIT
PIPELINED
ADC CORE
CLK A
CLK B
CLOCK/DUTY CYCLE
CONTROL
CLOCK/DUTY CYCLE
CONTROL
ANALOG
INPUT B
+
INPUT
S/H
12-BIT
PIPELINED
ADC CORE
OUTPUT
DRIVERS
OVDD
D11A
•••
D0A
OGND
OF
MUX
CLKOUT
OUTPUT
DRIVERS
OVDD
D11B
•••
D0B
OGND
2283 TA01
SNR vs Input Frequency,
–1dB, 2V Range
73
72
71
70
69
68
67
66
65
0 50 100 150 200 250 300 350
INPUT FREQUENCY (MHz) 2283 TA01b
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LTC2283
ABSOLUTE MAXIMUM RATINGS
OVDD = VDD (Notes 1, 2)
Supply Voltage (VDD) ..................................................4V
wwwD.diagtaitsahleOetu4utp.cuomt Ground Voltage (OGND) ........ –0.3V to 1V
Analog Input Voltage (Note 3).......–0.3V to (VDD + 0.3V)
Digital Input Voltage......................–0.3V to (VDD + 0.3V)
Digital Output Voltage ................ –0.3V to (OVDD + 0.3V)
Power Dissipation .............................................1500mW
Operating Temperature Range
LTC2283C ................................................ 0°C to 70°C
LTC2283I.............................................. –40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
PIN CONFIGURATION
TOP VIEW
AINA+ 1
AINA– 2
REFHA 3
REFHA 4
REFLA 5
REFLA 6
VDD 7
CLKA 8
CLKB 9
VDD 10
REFLB 11
REFLB 12
REFHB 13
REFHB 14
AINB– 15
AINB+ 16
65
48 DA5
47 DA4
46 DA3
45 DA2
44 DA1
43 DA0
42 NC
41 NC
40 CLKOUT
39 DB11
38 DB10
37 DB9
36 DB8
35 DB7
34 DB6
33 DB5
UP PACKAGE
64-LEAD (9mm × 9mm) PLASTIC QFN
TJMAX = 150°C, θJA = 20°C/W
EXPOSED PAD (PIN 65) IS GND AND MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2283CUP#PBF
LTC2283CUP#TRPBF LTC2283UP
64-Lead (9mm × 9mm) Plastic QFN
0°C to 70°C
LTC2283IUP#PBF
LTC2283IUP#TRPBF
LTC2283UP
64-Lead (9mm × 9mm) Plastic QFN
–40°C to 85°C
LEAD BASED FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2283CUP
LTC2283CUP#TR
LTC2283UP
64-Lead (9mm × 9mm) Plastic QFN
0°C to 70°C
LTC2283IUP
LTC2283IUP#TR
LTC2283UP
64-Lead (9mm × 9mm) Plastic QFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
PARAMETER
CONDITIONS
MIN TYP MAX
UNITS
Resolution (No Missing Codes)
12
Bits
Integral Linearity Error
Differential Analog Input (Note 5)
–2 ±0.4
2
LSB
Differential Linearity Error
Differential Analog Input
–0.9 ±0.2 0.9
LSB
Offset Error
(Note 6)
–12 ±2
12
mV
Gain Error
External Reference
–2.5 ±0.5 2.5
%FS
Offset Drift
±10 μV/°C
Full-Scale Drift
Internal Reference
±30 ppm/°C
External Reference
±5 ppm/°C
Gain Matching
External Reference
±0.3 %FS
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LTC2283
CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
PARAMETER
CONDITIONS
MIN TYP MAX
UNITS
Offset Matching
www.datasheet4u.com
Transition Noise
SENSE = 1V
±2 mV
0.32 LSBRMS
ANALOG INPUT The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
VIN
VIN,CM
Analog Input Range (AIN+ –AIN–)
Analog Input Common Mode (AIN+ +AIN–)/2
2.85V < VDD < 3.4V (Note 7)
±0.5V to ±1V
Differential Input Drive (Note 7)
1
1.5 1.9
Single Ended Input Drive (Note 7) 0.5
1.5
2
V
V
V
IIN Analog Input Leakage Current
0V < AIN+, AIN– < VDD
–1
1 μA
ISENSE
SENSEA, SENSEB Input Leakage
0V < SENSEA, SENSEB < 1V
–3
3 μA
IMODE
MODE Input Leakage Current
0V < MODE < VDD
–3
3 μA
tAP Sample-and-Hold Acquisition Delay Time
0 ns
tJITTER
Sample-and-Hold Acquisition Delay Time Jitter
0.2 psRMS
CMRR Analog Input Common Mode Rejection Ratio
80 dB
Full Power Bandwidth
Figure 8 Test Circuit
640 MHz
DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX
UNITS
SNR Signal-to-Noise Ratio
5MHz Input
70.2 dB
30MHz Input
70.1 dB
70MHz Input
68 70
dB
140MHz Input
69.6 dB
SFDR
Spurious Free Dynamic Range
2nd or 3rd Harmonic
5MHz Input
30MHz Input
88 dB
85 dB
70MHz Input
70 82
dB
140MHz Input
78 dB
SFDR
Spurious Free Dynamic Range
4th Harmonic or Higher
5MHz Input
30MHz Input
90 dB
90 dB
70MHz Input
77 90
dB
140MHz Input
90 dB
S/(N+D)
Signal-to-Noise Plus Distortion Ratio
5MHz Input
69.8 dB
30MHz Input
69.7 dB
70MHz Input
67 69.6
dB
140MHz Input
69.5 dB
IMD Intermodulation Distortion
Crosstalk
fIN = 40MHz, 41MHz
fIN = 100MHz
85 dB
–110 dB
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LTC2283
INTERNAL REFERENCE CHARACTERISTICS (Note 4)
PARAMETER
VCM Output Voltage
wwwV.dCaMtaOsuhtepeut4Tue.mcopmco
VCM Line Regulation
VCM Output Resistance
CONDITIONS
IOUT = 0
2.85V < VDD < 3.4V
|IOUT| < 1mA
MIN
1.475
TYP
1.500
±25
3
4
MAX
1.525
UNITS
V
ppm/°C
mV/V
Ω
DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
LOGIC INPUTS (CLK, OE, SHDN, MUX)
CONDITIONS
MIN TYP MAX
UNITS
VIH
VIL
IIN
CIN
LOGIC OUTPUTS
High Level Input Voltage
Low Level Input Voltage
Input Current
Input Capacitance
VDD = 3V
VDD = 3V
VIN = 0V to VDD
(Note 7)
2
–10
3
0.8
10
V
V
μA
pF
OVDD = 3V
COZ
ISOURCE
ISINK
VOH
VOL
OVDD = 2.5V
VOH
VOL
OVDD = 1.8V
VOH
VOL
Hi-Z Output Capacitance
Output Source Current
Output Sink Current
High Level Output Voltage
Low Level Output Voltage
High Level Output Voltage
Low Level Output Voltage
High Level Output Voltage
Low Level Output Voltage
OE = High (Note 7)
VOUT = 0V
VOUT = 3V
IO = –10μA
IO = –200μA
IO = 10μA
IO = 1.6mA
IO = –200μA
IO = 1.6mA
IO = –200μA
IO = 1.6mA
3
50
50
2.995
2.7 2.99
0.005
0.09
0.4
2.49
0.09
1.79
0.09
pF
mA
mA
V
V
V
V
V
V
V
V
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LTC2283
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 8)
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX
UNITS
VDD Analog Supply Voltage
wwwO.dVaDtDasheet4u.comOutput Supply Voltage
(Note 9)
(Note 9)
2.85
0.5
3
3
3.4
3.6
V
V
IVDD
PDISS
PSHDN
PNAP
Supply Current
Power Dissipation
Shutdown Power (Each Channel)
Nap Mode Power (Each Channel)
Both ADCs at fS(MAX)
Both ADCs at fS(MAX)
SHDN = H, OE = H, No CLK
SHDN = H, OE = L, No CLK
263 305
mA
790 915
mW
2 mW
15 mW
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
fs
tL
PARAMETER
Sampling Frequency
CLK Low Time
CONDITIONS
(Note 9)
Duty Cycle Stabilizer Off (Note 7)
Duty Cycle Stabilizer On (Note 7)
MIN TYP MAX
1
125
3.8 4 500
3
4 500
UNITS
MHz
ns
ns
tH CLK High Time
Duty Cycle Stabilizer Off (Note 7)
Duty Cycle Stabilizer On (Note 7)
3.8 4 500
3
4 500
ns
ns
tAP Sample-and-Hold Aperture Delay
tD CLK to DATA Delay
CL = 5pF (Note 7)
0
1.4 2.7 5.4
ns
ns
tC CLK to CLKOUT Delay
DATA to CLKOUT Skew
CL = 5pF (Note 7)
(tD – tC) (Note 7)
1.4 2.7 5.4
–0.6 0 0.6
ns
ns
tMD MUX to DATA Delay
Data Access Time After OE
CL = 5pF (Note 7)
CL = 5pF (Note 7)
1.4 2.7 5.4
4.3 10
ns
ns
BUS Relinquish Time
(Note 7)
3.3 8.5
ns
Pipeline Latency
5 Cycles
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = 3V, fSAMPLE = 125MHz, input range = 2VP-P with differential
drive, unless otherwise noted.
Note 5: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 0000 0000 0000 and 1111 1111 1111.
Note 7: Guaranteed by design, not subject to test.
Note 8: VDD = 3V, fSAMPLE = 125MHz, input range = 1VP-P with differential
drive. The supply current and power dissipation are the sum total for both
channels with both channels active.
Note 9: Recommended operating conditions.
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