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®
Data Sheet
March 6, 2009
ISL6260C
FN9259.2
Multiphase PWM Regulator for IMVP-6
Mobile CPUs
The ISL6260C is a multiple phase PWM buck regulator for
miroprocessor core power supply. The multiple phase
implementation results in better system performance, superior
thermal management, lower component cost, reduced power
dissipation, and smaller implementation area. The ISL6260C
multiphase controller together with ISL6208 external gate
drivers provide a complete solution to power Intel's mobile
microprocessors. The PWM modulator of ISL6260C is based
on Intersil's Robust Ripple Regulator technology (R3).
Compared with the traditional multiphase buck regulator, the R3
modulator commands variable switching frequency during load
transients, which achieves faster transient response. With the
same modulator, the switching frequency is reduced at light
load conditions resulting higher operation efficiency.
Intel Mobile Voltage Positioning (IMVP) reduces power
dissipation for Intel Pentium processors. The ISL6260C is
designed to be completely compliant with IMVP-6
specifications. ISL6260C responds to PSI# signal by adding or
dropping PWM2 and adjusting overcurrent protection
accordingly. To reduce audible noise, the DPRSLPVR signal
can be used to reduce output voltage slew rates when entering
and exiting Deeper Sleep State according to Intel specification.
The ISL6260C has several other key features. ISL6260C
reports output power through a power monitor pin. Current
sense can be achieved by using either inductor DCR or
discrete precision resistor. In the case of DCR current
sensing, a single NTC thermistor is used to thermally
compensate the inductor DCR variation with temperature. A
unity gain, differential amplifier is available for remote
voltage sensing. This allows the voltage on the CPU die to
be accurately regulated to meet Intel IMVP-6 specifications.
Features
• Precision Multiphase Core Voltage Regulation
- 0.5% System Accuracy Over Temperature
- Enhanced Load Line Accuracy
• Microprocessor Voltage Identification Input
- 7-Bit VID Input
- 0.300V to 1.500V in 12.5mV Steps
- Supports VID Changes On-The-Fly
• Multiple Current Sensing Approaches Supported
- Lossless DCR Current Sensing
- Precision Resistive Current Sensing
• Supports PSI# and Narrow VDC for Enhanced Battery Life
(EBL) Initiatives
• Superior Noise Immunity and Transient Response
• Power Monitor and Thermal Monitor
• Differential Remote Voltage Sensing
• High Efficiency Across Entire Load Range
• Programmable 1, 2 or 3 Power Channels
• Excellent Dynamic Current Balance between Channels
• Small Footprint 40 Ld 6x6 QFN Package
• Pb-Free Available (RoHS Compliant)
Applications
• Mobile Laptop Computers
Ordering Information
PART NUMBER
(Note)
PART MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL6260CCRZ
ISL6260 CCRZ
-10 to +100
40 Ld 6x6 QFN
L40.6x6
ISL6260CCRZ-T*
ISL6260 CCRZ
-10 to +100
40 Ld 6x6 QFN Tape and Reel
L40.6x6
ISL6260CIRZ
ISL6260 CIRZ
-40 to +100
40 Ld 6x6 QFN
L40.6x6
ISL6260CIRZ-T*
ISL6260 CIRZ
-40 to +100
40 Ld 6x6 QFN Tape and Reel
L40.6x6
*Please refer to TB347 for details on reel specifications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2006, 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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ISL6260C
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ISL6260C
(40 LD QFN)
TOP VIEW
40 39 38 37 36 35 34 33 32 31
PSI# 1
PMON 2
RBIAS 3
VR_TT# 4
NTC 5
SOFT 6
OCSET 7
VW 8
COMP 9
FB 10
GND PAD
(BOTTOM)
30 VID2
29 VID1
28 VID0
27 PWM1
26 PWM2
25 PWM3
24 FCCM
23 ISEN1
22 ISEN2
21 ISEN3
11 12 13 14 15 16 17 18 19 20
Functional Pin Description
PSI#
Low load current indicator input. When asserted low,
indicates a reduced load-current condition. For ISL6260C,
when PSI# is asserted low, PWM2 will be disabled.
PMON
An analog output. PMON sends out an analog signal
proportional to the product of VCCSENSE voltage and the
droop voltage.
RBIAS
147k Resistor to VSS sets internal current reference.
VR_TT#
Thermal overload output indicator.
NTC
Thermistor input to VR_TT# circuit.
SOFT
A capacitor from this pin to Vss sets the maximum slew rate
of the output voltage. It affects both soft start and VID
transitioning slew rate. Soft pin is the non-inverting input of
the error amplifier.
OCSET
Overcurrent set input. A resistor from this pin to VO sets
DROOP voltage limit for OC trip. A 10µA current source is
connected internally to this pin.
VW
A resistor from this pin to COMP programs the switching
frequency. (7kΩ gives approximately 300kHz). VW pin
sources current.
COMP
This pin is the output of the error amplifier.
FB
This pin is the inverting input of error amplifier.
VDIFF
This pin is the output of the differential amplifier.
VSEN
Remote core voltage sense input. Connect to
microprocessor die.
RTN
Remote voltage sensing return. Connect to ground at
microprocessor die.
DROOP
Output of droop amplifier. Output = VO + DROOP.
DFB
Inverting input to droop amplifier.
VO
An input to the IC that reports the local output voltage.
VSUM
This pin is connected to the current summation junction.
VIN
Battery supply voltage, used for feed forward.
VSS
Signal ground; Connect to local controller ground.
VDD
5V bias power.
ISEN3
Individual current sensing for channel 3.
ISEN2
Individual current sensing for channel 2.
ISEN1
Individual current sensing for channel 1.
FCCM
Forced Continuous Conduction Mode (FCCM) enable pin to
MOSFET drivers. It will disable diode emulation.
2 FN9259.2
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ISL6260C
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PWM output for channel 3. When PWM3 is pulled to 5V
VDD, PWM3 will be disabled and allow other channels to
operate.
PWM2
PWM output for channel 2. For ISL6260C, PSI# low will
make this output tri-state. When PWM2 is pulled to 5V VDD,
PWM2 will be disabled and allow other channels to operate.
PWM1
PWM output for channel 1.
VID0, VID1, VID2, VID3, VID4, VID5, VID6
VID input with VID0 = LSB and VID6 = MSB.
CLK_EN#
Digital output to enable System PLL Clock; Goes active after
13 switching cycles after Vcore is within 10% of Boot
Voltage.
PGOOD
Power Good open-drain output. Will be pulled up externally
by a 680Ω resistor to VCCP or 1.9kΩ to 3.3V.
3V3
3.3V supply voltage for CLK_EN# logic, such an
implementation will improve power consumption from 3.3V
compared to open drain circuit other wise.
VR_ON
Voltage Regulator enable input. A high level logic signal on
this pin enables the regulator.
DPRSLPVR
Deeper Sleep Enable signal. At steady state, a high level
logic signal on this pin indicates that the micro-processor is
in Deeper Sleep Mode. Between active and sleep mode
transition, high logic level on this pin programs slow C4 entry
and exit; low logic level on this pin programs large charging
or discharging soft pin current, and therefore fast output
voltage transition slew rate.
DPRSTP#
Deeper Sleep Enable signal. A low level logic signal on this
pin indicates that the micro-processor is in Deeper Sleep
Mode.
3 FN9259.2
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ISL6260C
www.ADabtasSohleuette4UM.caomximum Ratings
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +7V
Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25V
Open Drain Outputs, PGOOD, VR_TT# . . . . . . . . . . . . -0.3 to +7V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to (VDD + 0.3V)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +100°C
Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . . . . +5V ±5%
Thermal Information
Thermal Resistance (Notes 1, 2)
θJA (°C/W) θJC (°C/W)
QFN Package. . . . . . . . . . . . . . . . . . . .
30
5.5
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Operating Conditions: VDD = 5V, TA = -40°C to +100°C, unless otherwise noted. Parameters with MIN and/or
MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
INPUT POWER SUPPLY
+5V Supply Current
IVDD
VR_ON = 3.3V
VR_ON = 0V
3.6 4.2 mA
1 µA
+3.3V Supply Current
Battery Supply Current
VIN Input Resistance
Power-On-Reset Threshold
SYSTEM AND REFERENCES
I3V3
IVIN
RVIN
PORr
PORf
No load on CLK_EN#
VR_ON = 0V
VR_ON = 3.3V
VDD rising
VDD falling
VDD falling, TA = -10°C to +100°C
3.95
4.00
900
4.35
4.15
4.15
1
1
4.5
µA
µA
kΩ
V
V
V
System Accuracy
%Error
(VCC_CORE)
No load; closed loop, active mode range
VID = 0.75V - 1.50V
No load; closed loop, active mode range
VID = 0.75V - 1.50V, TA = -10°C to +100°C
VID = 0.5V - 0.7375V
-0.8
-0.5
-10
+0.8
+0.5
+10
%
%
mV
VID = 0.5V - 0.7375V, TA = -10°C to +100°C
VID = 0.3 - 0.4875V
-8
-18
+8 mV
+18 mV
VBOOT
Maximum Output Voltage
Minimum Output Voltage
VID Off State
VID = 0.3 - 0.4875V, TA = -10°C to +100°C
VCC_CORE(max) VID = [0000000]
VCC_CORE(min) VID = [1100000]
VID = [1111111]
-15
1.176
1.200
1.500
0.300
0.0
+15
1.224
mV
V
V
V
V
RBIAS Voltage
CHANNEL FREQUENCY
RBIAS = 147kΩ
1.45 1.47 1.49
V
Nominal Channel Frequency
Adjustment Range
AMPLIFIERS
fSW(nom) Rfset = 7kΩ, 3 channel operation, VCOMP = 2V 285 300 315 kHz
See Equation 4 RFSET selection
200 500 kHz
Droop Amplifier Offset
-0.3
+0.3
mV
Error Amp DC Gain
Error Amp Gain-Bandwidth Product
Av0
GBW
(Note 3)
CL= 20pF (Note 3)
90 dB
18 MHz
4 FN9259.2
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ISL6260C
www.EDaletacSthreiceta4lUS.cpomecifications
Operating Conditions: VDD = 5V, TA = -40°C to +100°C, unless otherwise noted. Parameters with MIN and/or
MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
FB Input Current
ISEN
IIN(FB)
10 150 nA
Imbalance Voltage
Maximum of ISENs - Minimum of ISENs
2 mV
Input Bias Current
20 nA
SOFT CURRENT
Soft-start Current
ISS
SOFT Geyserville Current
IGV
SOFT Deeper Sleep Entry Current
IC4
SOFT Deeper Sleep Exit Current
IC4EA
SOFT Deeper Sleep Exit Current
IC4EB
POWER GOOD AND PROTECTION MONITORS
|SOFT-VDAC| >100mV
DPRSLPVR = 3.3V
DPRSLPVR = 3.3V
DPRSLPVR = 0V
-47
±180
-47
37
180
-42
±205
-42
42
205
-37
±230
-37
47
230
µA
µA
µA
µA
µA
PGOOD Low Voltage
PGOOD Leakage Current
PGOOD Delay
VOL
IOH
tpgd
IPGOOD= 4mA
PGOOD = 3.3V
CLK_ENABLE# LOW to PGOOD HIGH
0.26 0.4
-1 1
6.3 7.6 8.9
V
µA
ms
Overvoltage Threshold
Severe Overvoltage Threshold
OCSET Reference Current
OC Threshold Offset
OVH
OVHS
VO rising above setpoint for >1ms
VO rising for >2µs
I(RBIAS) = 10µA
DROOP rising above OCSET for >150µs
160 200 240 mV
1.675 1.7 1.725
V
9.8 10 10.2 µA
-2 4 mV
Current Imbalance Threshold
One ISEN above another ISEN for >1.2ms
9 mV
Undervoltage Threshold
(VDIFF/SOFT)
UVf VO falling below setpoint for >1.2ms
-355 -295 -235
mV
LOGIC THRESHOLDS
VR_ON and DPRSLPVR Input Low
VR_ON and DPRSLPVR Input High
VID0-VID6, PSI#, DPRSTP# Input
Low
VIL(3.3V)
VIH(3.3V)
VIL(1.0V)
1.0 V
2.3 V
0.3 V
VID0-VID6, PSI#, DPRSTP# Input
High
VIH(1.0V)
0.7 V
PWM
PWM (PWM1-PWM3) Output Low
FCCM Output Low
VOL(5.0V)
VOL_FCCM
Sinking 5mA
Sinking 3mA
1.0 V
1.0 V
PWM (PWM1-PWM3) and FCCM
Output High
VOH(5.0V) Sourcing 5mA
3.5 V
PWM Tri-State Leakage
PWM = 2.5V
-1 1 µA
THERMAL MONITOR
NTC Source Current
NTC = 1.3V
53 60 67 µA
Over-Temperature Threshold
V (NTC) falling
1.18 1.2 1.22
V
VR_TT# Low Output Resistance
CLK_EN# OUTPUT LEVELS
RTT I = 20mA
6.5 9
Ω
CLK_EN# High Output Voltage
CLK_EN# Low Output Voltage
POWER MONITOR
VOH
VOL
3V3 = 3.3V, I = -4mA
I = 4mA
2.9 3.1
0.26 0.4
V
V
PMON Output Voltage
Vpmon
VSEN = 1.2V, Droop-Vo = 80mV
1.638 1.68 1.722
V
VSEN = 1.0V, Droop-Vo = 20mV
0.308 0.35 0.392
V
5 FN9259.2
March 6, 2009