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P89LPC9301/931A1
8-bit microcontroller with accelerated two-clock 80C51 core
4 kB/8 kB 3 V byte-erasable flash
Rev. 01 — 9 April 2009
Preliminary data sheet
1. General description
The P89LPC9301/931A1 is a single-chip microcontroller, available in low cost packages,
based on a high performance processor architecture that executes instructions in two to
four clocks, six times the rate of standard 80C51 devices. Many system-level functions
have been incorporated into the P89LPC9301/931A1 in order to reduce component count,
board space, and system cost.
2. Features
2.1 Principal features
I 4 kB/8 kB byte-erasable flash code memory organized into 1 kB sectors and 64-byte
pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage.
I 256-byte RAM data memory.
I Two analog comparators with selectable inputs and reference source.
I Two 16-bit counter/timers (each may be configured to toggle a port output upon timer
overflow or to become a PWM output).
I A 23-bit system timer that can also be used as real-time clock consisting of a 7-bit
prescaler and a programmable and readable 16-bit timer.
I Enhanced UART with a fractional baud rate generator, break detect, framing error
detection, and automatic address detection; 400 kHz byte-wide I2C-bus
communication port and SPI communication port.
I 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or
driven to 5.5 V).
I Enhanced low voltage (brownout) detect allows a graceful system shutdown when
power fails.
I 28-pin TSSOP and PLCC packages with 23 I/O pins minimum and up to 26 I/O pins
while using on-chip oscillator and reset options.
2.2 Additional features
I A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns
for all instructions except multiply and divide when executing at 18 MHz. This is six
times the performance of the standard 80C51 running at the same clock frequency. A
lower clock frequency for the same performance results in power savings and reduced
EMI.
I Serial flash In-Circuit Programming (ICP) allows simple production coding with
commercial EPROM programmers. Flash security bits prevent reading of sensitive
application programs.

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P89LPC9301/931A1
8-bit microcontroller with accelerated two-clock 80C51 core
I Serial flash In-System Programming (ISP) allows coding while the device is mounted
in the end application.
I In-Application Programming (IAP) of the flash code memory. This allows changing the
code in a running application.
I Watchdog timer with separate on-chip oscillator, nominal 400 kHz, calibrated to ±5 %,
requiring no external components. The watchdog prescaler is selectable from
eight values.
I High-accuracy internal RC oscillator option, with clock doubler option, allows operation
without external oscillator components. The RC oscillator option is selectable and fine
tunable.
I Switching on the fly among internal RC oscillator, watchdog oscillator, external clock
source provides optimal support of minimal power active mode with fast switching to
maximum performance.
I Idle and two different power-down reduced power modes. Improved wake-up from
Power-down mode (a LOW interrupt input starts execution). Typical power-down
current is 1 µA (total power-down with voltage comparators disabled).
I Active-LOW reset. On-chip power-on reset allows operation without external reset
components. A software reset function is also available.
I Configurable on-chip oscillator with frequency range options selected by user
programmed flash configuration bits. Oscillator options support frequencies from
20 kHz to the maximum operating frequency of 18 MHz.
I Oscillator fail detect. The watchdog timer has a separate fully on-chip oscillator
allowing it to perform an oscillator fail detect function.
I Programmable port output configuration options: quasi-bidirectional, open drain,
push-pull, input-only.
I High current sourcing/sinking (20 mA) on eight I/O pins (P0.3 to P0.7, P1.4, P1.6,
P1.7). All other port pins have high sinking capability (20 mA). A maximum limit is
specified for the entire chip.
I Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value of
the pins match or do not match a programmable pattern.
I Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns
minimum ramp times.
I Only power and ground connections are required to operate the P89LPC9301/931A1
when internal reset option is selected.
I Four interrupt priority levels.
I Eight keypad interrupt inputs, plus two additional external interrupt inputs.
I Schmitt trigger port inputs.
I Second data pointer.
I Emulation support.
P89LPC9301_931A1_1
Preliminary data sheet
Rev. 01 — 9 April 2009
© NXP B.V. 2009. All rights reserved.
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P89LPC9301/931A1
8-bit microcontroller with accelerated two-clock 80C51 core
3. Ordering information
Table 1. Ordering information
Type number
Package
Name
Description
P89LPC9301FDH
TSSOP28 plastic thin shrink small outline package; 28
leads; body width 4.4 mm
P89LPC931A1FDH TSSOP28 plastic thin shrink small outline package; 28
leads; body width 4.4 mm
Version
SOT361-1
SOT361-1
3.1 Ordering options
Table 2. Ordering options
Type number
Flash memory
P89LPC9301FDH
4 kB
P89LPC931A1FDH 8 kB
Temperature range
40 °C to +85 °C
40 °C to +85 °C
Frequency
0 MHz to 18 MHz
0 MHz to 18 MHz
P89LPC9301_931A1_1
Preliminary data sheet
Rev. 01 — 9 April 2009
© NXP B.V. 2009. All rights reserved.
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