AT91SAM9RL64.pdf 데이터시트 (총 30 페이지) - 파일 다운로드 AT91SAM9RL64 데이타시트 다운로드

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Features
Incorporates the ARM926EJ-SARM® Thumb® Processor
– DSP Instruction Extensions
– ARM Jazelle® Technology for Java® Acceleration
– 4 Kbyte Data Cache, 4 Kbyte Instruction Cache, Write Buffer
– 220 MIPS at 200 MHz
– Memory Management Unit
– EmbeddedICEIn-circuit Emulation, Debug Communication Channel Support
Multi-layer AHB Bus Matrix for Large Bandwidth Transfers
– Six 32-bit-layer Matrix
– Boot Mode Select Option, Remap Command
One 32-KByte internal ROM, Single-cycle Access at Maximum Speed
One 64-KByte internal SRAM, Single-cycle Access at Maximum Speed
– 4 Blocks of 16 Kbytes Configurable in TCM or General-purpose SRAM on the AHB
Bus Matrix
– Single-cycle Accessible on AHB Bus at Bus Speed
– Single-cycle Accessible on TCM Interface at Processor Speed
2-channel DMA
– Memory to Memory Transfer
– 16 Bytes FIFO
– LInked List
External Bus Interface (EBI)
– EBI Supports SDRAM, Static Memory, ECC-enabled NAND Flash and
CompactFlash®
LCD Controller (for AT91SAM9RL64 only)
– Supports Passive or Active Displays
– Up to 24 Bits per Pixel in TFT Mode, Up to 16 bits per Pixel in STN Color Mode
– Up to 16M Colors in TFT Mode, Resolution Up to 2048x2048, Virtual Screen
Support
High Speed (480 Mbit/s) USB 2.0 Device Controller
– On-Chip High Speed Transceiver, UTMI+ Physical Interface
– Integrated FIFOs and Dedicated DMA
– 4 Kbyte Configurable Integrated DPRAM
Fully-featured System Controller, including
– Reset Controller, Shutdown Controller
– Four 32-bit Battery Backup Registers for a Total of 16 Bytes
– Clock Generator and Power Management Controller
– Advanced Interrupt Controller and Debug Unit
– Periodic Interval Timer, Watchdog Timer and Real-time Timer and Real-time Clock
Reset Controller (RSTC)
– Based on Two Power-on Reset Cells
– Reset Source Identification and Reset Output Control
Shutdown Controller (SHDC)
– Programmable Shutdown Pin Control and Wake-up Circuitry
Clock Generator (CKGR)
– Selectable 32768 Hz Low-power Oscillator or Internal Low-power RC Oscillator on
Battery Backup Power Supply, Providing a Permanent Slow Clock
– 12 MHz On-chip Oscillator for Main System Clock and USB Clock
– One PLL up to 240 MHz
AT91SAM
ARM-based
Embedded MPU
AT91SAM9R64
AT91SAM9RL64
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– One PLL 480 MHz Optimized for USB HS
Power Management Controller (PMC)
– Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities
– Two Programmable External Clock Signals
Advanced Interrupt Controller (AIC)
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
– One External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected
Debug Unit (DBGU)
– 2-wire UART and Support for Debug Communication Channel, Programmable ICE Access Prevention
– Mode for General Purpose 2-wire UART Serial Communication
Periodic Interval Timer (PIT)
– 20-bit Interval Timer plus 12-bit Interval Counter
Watchdog Timer (WDT)
– Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock
Real-time Timer (RTT)
– 32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler
Real-time Clock (RTC)
– Time, Date and Alarm 32-bit Parallel Load
– Low Power Consumption
– Programmable Periodic Interrupt
One 6-channel 10-Bit Analog-to-Digital Converter
– Touch Screen Interface Compatible with Industry Standard 4-wire Sensitive Touch Panels
Four 32-bit Parallel Input/Output Controllers (PIOA, PIOB, PIOC and PIOD)
– 118 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os for 217-ball BGA Package
– Input Change Interrupt Capability on Each I/O Line
– Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output
22-channel Peripheral DMA Controller (PDC)
One MultiMedia Card Interface (MCI)
– SDCard/SDIO 1.0 and MultiMediaCard4.3 Compliant
– Automatic Protocol Control and Fast Automatic Data Transfers with PDC
Two Synchronous Serial Controllers (SSC)
– Independent Clock and Frame Sync Signals for Each Receiver and Transmitter
– I²S Analog Interface Support, Time Division Multiplex Support
– High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
One AC97 Controller (AC97C)
– 6-channel Single AC97 Analog Front End Interface, Slot Assigner
Four Universal Synchronous/Asynchronous Receiver Transmitters (USART)
– Individual Baud Rate Generator, IrDA® Infrared Modulation/Demodulation, Manchester Encoding/Decoding
– Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support
One Master/Slave Serial Peripheral Interface (SPI)
– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
– High-speed Synchronous Communications
One Three-channel 16-bit Timer/Counter (TC)
– Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel
– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
One Four-channel 16-bit PWM Controller (PWMC)
Two Two-wire Interfaces (TWI)
– Compatible with Standard Two-wire Serial Memories
– One, Two or Three Bytes for Slave Address
– Sequential Read/Write Operations
2 AT91SAM9R64/RL64
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AT91SAM9R64/RL64
– Master, Multi-master and Slave Mode Operation
– Bit Rate: Up to 400 Kbits
– General Call Supported in Slave Mode
– Connection to Peripheral DMA Controller (PDC) Channel Capabilities Optimizes Data Transfers in Master Mode Only
(TWI0 only)
SAM-BA® Boot Assistant
– Default Boot Program
– Interface with SAM-BA Graphic User Interface
IEEE® 1149.1 JTAG Boundary Scan on All Digital Pins
Required Power Supplies:
– 1.08 to 1.32V for VDDCORE, VDDUTMIC, VDDPLLB and VDDBU
– 3.0V to 3.6V for VDDPLLA, VDDANA, VDDUTMII and VDDIOP
– Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOM
Available in a 144-ball BGA (AT91SAM9R64) and a 217-ball LFBGA (AT91SAM9RL64) Package
1. Description
The AT91SAM9R64/RL64 device is based on the integration of an ARM926EJ-S processor with
a large fast SRAM and a wide range of peripherals.
The AT91SAM9R64/RL64 embeds one USB Device High Speed Controller, one LCD Controller
(for AT91SAM9RL64 only), one AC97 controller, a 2-channel DMA Controller, four USARTs, two
SSCs, one SPI, two TWIs, three Timer Counter channels, a 4-channel PWM generator, one Mul-
timedia Card interface and a 6-channel Analog-to-digital converter that also provides resistive
touch screen management.
The AT91SAM9R64/RL64 is architectured on a 6-layer bus matrix. It also features an External
Bus Interface capable of interfacing with a wide range of memory and peripheral devices.
Some features are not available for AT91SAM9R64 in the 144-ball BGA package.
Separate block diagrams and PIO multiplexing are provided in this document. Table 1-1 lists the
features and signals of AT91SAM9RL64 that are not available or partially available for
AT91SAM9R64. When the signal is multiplexed on a PIO, the PIO line is specified.
Table 1-1.
Feature
AC97
EBI
LCDC
Unavailable or Partially Available Features and Signals in AT91SAM9R64
Full/Partial
Signal
Peripheral A
Peripheral B
AC97FS
AC97CK
Full
AC97TX
AC97RX
PD1
PD2
-
PD3
PD4
Partial
D16-D31
NCS2
NCS5/CFCS1
PB16-PB31
PD0
PD13
-
LCDMOD
PC2
LCDCC
PC3
LCDVSYNC
PC4
Full LCDHSYNC PC5
-
LCDDOTCK
PC6
LCDDEN
PC7
LCDD0-LCDD23
PC8-PC31
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Table 1-1. Unavailable or Partially Available Features and Signals in AT91SAM9R64
Feature
Full/Partial
Signal
Peripheral A
Peripheral B
PWM
Partial
PWM2
PD5 and PD12
-
NPCS2
SPI Partial
NPCS3
PD8
PD9 and PD13
SSC1
Full
RF1
RK1
TD1
RD1
TK1
TF1
PA8
PA9
PA13
-
PA14
PA29
PA30
Touchscreen
ADC
Partial
AD3YM
GPAD4
GPAD5
PA20
PD6
PD7
-
TIOA1
TIOB1
TC
Partial
TCLK1
TIOA2
TIOB2
-
PC29
PC30
PC31
PD10
PD11
TWI Full
TWD1
TWCK1
PD10
PD11
-
USART0
Partial
SCK0
RTS0
CTS0
DSR0
DTR0
DCD0
RI0
PA8
PA9
PA10
PD14
PD15
PD16
PD17
-
USART1
Partial
SCK1
-
PD2
USART2
Partial
SCK2
RTS2
CTS2
PD9
PA29
PA30
-
SCK3
PA20
USART3
Partial
RTS3
-
PD3
CTS3
PD4
4 AT91SAM9R64/RL64
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2. Block Diagrams
Figure 2-1. AT91SAM9R64 Block Diagram
AT91SAM9R64/RL64
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