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Multiphase PWM Regulator for IMVP-6.5™ Mobile CPUs
and GPUs
ISL62882, ISL62882B
The ISL62882 is a multiphase PWM buck regulator for
miroprocessor or graphics processor core power supply. The
multiphase buck converter uses interleaved phases to reduce the
total output voltage ripple with each phase carrying a portion of the
total load current, providing better system performance, superior
thermal management, lower component cost, reduced power
dissipation, and smaller implementation area. The ISL62882 uses
two integrated gate drivers to provide a complete solution. The PWM
modulator is based on Intersil's Robust Ripple Regulator (R3)
technology™. Compared with traditional modulators, the R3
modulator commands variable switching frequency during load
transients, achieving faster transient response. With the same
modulator, the switching frequency is reduced at light load,
increasing the regulator efficiency.
The ISL62882 can be configured as CPU or graphics Vcore controller
and is fully compliant with IMVP-6.5™ specifications. It responds to
PSI# and DPRSLPVR signals by adding or dropping Phase 2,
adjusting overcurrent protection threshold accordingly, and
entering/exiting diode emulation mode. It reports the regulator
output current through the IMON pin. It senses the current by using
either discrete resistor or inductor DCR whose variation over
temperature can be thermally compensated by a single NTC
thermistor. It uses differential remote voltage sensing to accurately
regulate the processor die voltage. The unique split LGATE function
further increases light load efficiency. The adaptive body diode
conduction time reduction function minimizes the body diode
conduction loss in diode emulation mode. User-selectable overshoot
reduction function offers an option to aggressively reduce the output
capacitors as well as the option to disable it for users concerned
about increased system thermal stress. The ISL62882 offers the
FB2 function to optimize 1-phase performance.
The ISL62882B has the same functions as the ISL62882, but
comes in a different package.
Features
• Programmable 1- or 2-Phase CPU Mode Operation or 1-Phase
GPU Mode Operation
• Precision Multiphase Core Voltage Regulation
- 0.5% System Accuracy Over-Temperature
- Enhanced Load Line Accuracy
• Microprocessor Voltage Identification Input
- 7-Bit VID Input, 0V to 1.500V in 12.5mV Steps
- Supports VID Changes On-The-Fly
• Supports Multiple Current Sensing Methods
- Lossless Inductor DCR Current Sensing
- Precision Resistor Current Sensing
• Supports PSI# and DPRSLPVR modes
• Superior Noise Immunity and Transient Response
• Current Monitor and Thermal Monitor
• Differential Remote Voltage Sensing
• High Efficiency Across Entire Load Range
• Programmable 1- or 2-Phase Operation
• Two Integrated Gate Drivers
• Excellent Dynamic Current Balance Between Phases
• Split LGATE1 Drivers Increases Light Load Efficiency
• FB2 Function Optimizes 1-Phase Mode Performance
• Adaptive Body Diode Conduction Time Reduction
• User-selectable Overshoot Reduction Function
• Small Footprint 40 Ld 5x5 or 48 Ld 6x6 TQFN Packages
• Pb-Free (RoHS Compliant)
Applications
• Notebook Core Voltage Regulator
• Notebook GPU Voltage Regulator
June 21, 2011
FN6890.4
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2009-2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.

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ISL62882, ISL62882B
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL62882IRTZ
62882 IRTZ
-40 to +100
40 Ld 5x5 TQFN
L40.5x5
ISL62882HRTZ
62882 HRTZ
-10 to +100
40 Ld 5x5 TQFN
L40.5x5
ISL62882BHRTZ
62882 BHRTZ
-10 to +100
48 Ld 6x6 TQFN
L48.6x6
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL62882, ISL62882B. For more information on MSL please see techbrief
TB363.
Pin Configurations
ISL62882
(40 LD TQFN)
TOP VIEW
ISL62882B
(48 LD TQFN)
TOP VIEW
40 39 38 37 36 35 34 33 32 31
PGOOD 1
PSI# 2
RBIAS 3
VR_TT# 4
NTC 5
VW 6
COMP 7
FB 8
FB2 9
ISEN2 10
GND PAD
(BOTTOM)
30 BOOT2
29 UGATE2
28 PHASE2
27 VSSP2
26 LGATE2
25 VCCP
24 LGATE1b
23 LGATE1a
22 VSSP1
21 PHASE1
11 12 13 14 15 16 17 18 19 20
48 47 46 45 44 43 42 41 40 39 38 37
NC 1
PGOOD 2
PSI# 3
RBIAS 4
VR_TT# 5
NTC 6
GND 7
VW 8
COMP 9
FB 10
FB2 11
NC 12
(BOTTOM)
36 BOOT2
35 UGATE2
34 PHASE2
33 VSSP2
32 LGATE2
31 NC
30 VCCP
29 LGATE1b
28 LGATE1a
27 VSSP1
26 PHASE1
25 UGATE1
13 14 15 16 17 18 19 20 21 22 23 24
2 FN6890.4
June 21, 2011

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ISL62882, ISL62882B
Functional Pin Descriptions
ISL62882
-
1
ISL62882B
7
2
23
34
45
56
68
79
8 10
9 11
10
11
12
13
14, 15
16
17
18
19
13
14
15
16
17, 18
19
20
22
24
20 25
21 26
22 27
23 28
24 29
--
SYMBOL
GND
PGOOD
PSI#
RBIAS
VR_TT#
NTC
VW
COMP
FB
FB2
ISEN2
ISEN1
VSEN
RTN
ISUM- and ISUM+
VDD
VIN
IMON
BOOT1
UGATE1
PHASE1
VSSP1
LGATE1a
LGATE1b
LGATE1
DESCRIPTION
Signal common of the IC. Unless otherwise stated, signals are referenced to the GND pin.
Power-Good open-drain output indicating when the regulator is able to supply regulated voltage.
Pull-up externally with a 680Ω resistor to VCCP or 1.9kΩ to 3.3V.
Low load current indicator input. When asserted low, indicates a reduced load current condition.
A resistor to GND sets internal current reference. Use 147kΩ or 47kΩ. The choice of Rbias value,
together with the ISEN2 pin configuration and the external resistance from the COMP pin to GND,
programs the controller to enable/disable the overshoot reduction function and to select the
CPU/GPU mode.
Thermal overload output indicator.
Thermistor input to VR_TT# circuit.
A resistor from this pin to COMP programs the switching frequency (8kΩ gives approximately
300kHz).
This pin is the output of the error amplifier. Also, a resistor across this pin and GND adjusts the
overcurrent threshold.
This pin is the inverting input of the error amplifier.
There is a switch between the FB2 pin and the FB pin. The switch is on in 2-phase mode and is
off in 1-phase mode. The components connecting to FB2 are used to adjust the compensation
in 1-phase mode to achieve optimum performance.
Individual current sensing for Phase 2. When ISEN2 is pulled to 5V VDD, the controller will
disable Phase 2.
Individual current sensing for phase 1.
Remote core voltage sense input. Connect to microprocessor die.
Remote voltage sensing return. Connect to ground at microprocessor die.
Droop current sense input.
5V bias power.
Battery supply voltage, used for feed-forward.
An analog output. IMON outputs a current proportional to the regulator output current.
Connect an MLCC capacitor across the BOOT1 and the PHASE1 pins. The boot capacitor is
charged through an internal boot diode connected from the VCCP pin to the BOOT1 pin, each
time the PHASE1 pin drops below VCCP minus the voltage dropped across the internal boot
diode.
Output of the Phase-1 high-side MOSFET gate driver. Connect the UGATE1 pin to the gate of the
Phase-1 high-side MOSFET.
Current return path for the Phase-1 high-side MOSFET gate driver. Connect the PHASE1 pin to the
node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output
inductor of Phase-1.
Current return path for the Phase-1 low-side MOSFET gate driver. Connect the VSSP1 pin to the
source of the Phase-1 low-side MOSFET through a low impedance path, preferably in parallel
with the traces connecting the LGATE1a and the LGATE1b pins to the gates of the Phase-1
low-side MOSFETs.
Output of the Phase-1 low-side MOSFET gate driver that is always active. Connect the LGATE1a
pin to the gate of the Phase-1 low-side MOSFET that is active all the time.
Another output of the Phase-1 low-side MOSFET gate driver. This gate driver will be pulled low
when the DPRSLPVR pin logic is high. Connect the LGATE1b pin to the gate of the Phase-1
low-side MOSFET that is idle in deeper sleep mode.
Output of the Phase-1 low-side MOSFET gate driver. Connect the LGATE1 pin to the gate of the
Phase-1 low-side MOSFET.
3 FN6890.4
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ISL62882, ISL62882B
Functional Pin Descriptions (Continued)
ISL62882
25
ISL62882B
30
26 32
27 33
28 34
29 35
30 36
31 thru 37
38
39
38 thru 44
45
46
40 47
- 48
pad pad
SYMBOL
VCCP
LGATE2
VSSP2
PHASE2
UGATE2
BOOT2
VID0 thru VID6
VR_ON
DPRSLPVR
CLK_EN#
NC
BOTTOM
DESCRIPTION
Input voltage bias for the internal gate drivers. Connect +5V to the VCCP pin. Decouple with at
least 1µF of an MLCC capacitor to VSSP1 and VSSP2 pins respectively.
Output of the Phase-2 low-side MOSFET gate driver. Connect the LGATE2 pin to the gate of the
Phase-2 low-side MOSFET.
Current return path for the Phase-2 converter low-side MOSFET gate driver. Connect the VSSP2
pin to the source of the Phase-2 low-side MOSFET through a low impedance path, preferably in
parallel with the trace connecting the LGATE2 pin to the gate of the Phase-2 low-side MOSFET.
Current return path for the Phase-2 high-side MOSFET gate driver. Connect the PHASE2 pin to the
node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output
inductor of Phase-2.
Output of the Phase-2 high-side MOSFET gate driver. Connect the UGATE2 pin to the gate of the
Phase-2 high-side MOSFET.
Connect an MLCC capacitor across the BOOT2 and the PHASE2 pins. The boot capacitor is
charged through an internal boot diode connected from the VCCP pin to the BOOT2 pin, each
time the PHASE2 pin drops below VCCP minus the voltage dropped across the internal boot
diode.
VID input with VID0 = LSB and VID6 = MSB.
Voltage regulator enable input. A high level logic signal on this pin enables the regulator.
Deeper sleep enable signal. A high level logic signal on this pin indicates that the microprocessor
is in deeper sleep mode.
Open drain output to enable system PLL clock. It goes low 13 switching cycles after Vcore is
within 10% of Vboot.
No connect.
The bottom pad of ISL62882B is electrically connected to the GND pin inside the IC.
4 FN6890.4
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Block Diagram
ISL62882, ISL62882B
VIN VSEN ISEN2
ISEN1 PGOOD CLK_EN#
VDD
VR_ON
PSI#
DPRSLPVR
RBIAS
VID0
VID1
VID2
VID3
VID4
VID5
VID6
RTN
FB
COMP
VW
FB2
IMON
ISUM+
ISUM-
MODE
CONTROL
DAC
AND
SOFT-
START
CURRENT
BALANCE
IBAL
PGOOD &
CLK_EN#
LOGIC
PROTECTION FLT
WOC OC
VIN
CLOCK
IBAL VIN VDAC
MODULATOR
VDAC
COMP
VW
COMP
6µA 54µA 1.20V
1.24V
DRIVER
SHOOT THROUGH
PROTECTION
DRIVER
Σ
E/A
IDROOP
IMON
CURRENT
SENSE
2.5X
DRIVER
IBAL VIN VDAC
MODULATOR
WOC
COMP
CURRENT
COMPARATORS
NUMBER OF
OC PHASES
60µA
GAIN
SELECT
Σ
SHOOT THROUGH
PROTECTION
DRIVER
DRIVER
ADJ. OCP
THRESHOLD
COMP
VR_TT#
NTC
BOOT2
UGATE2
PHASE2
LGATE2
VSSP2
BOOT1
UGATE1
PHASE1
VCCP
LGATE1A
VSSP1
LGATE1B
GND
5 FN6890.4
June 21, 2011