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Multiphase PWM Regulator for IMVP-6.5™ Mobile CPUs
ISL62883, ISL62883B
The ISL62883 is a multiphase PWM buck regulator for
miroprocessor core power supply. The multiphase buck converter
uses interleaved phase to reduce the total output voltage ripple with
each phase carrying a portion of the total load current, providing
better system performance, superior thermal management, lower
component cost, reduced power dissipation, and smaller
implementation area. The ISL62883 uses two integrated gate
drivers and an external gate driver to provide a complete solution.
The PWM modulator is based on Intersil's Robust Ripple Regulator
(R3) technology™. Compared with traditional modulators, the R3
modulator commands variable switching frequency during load
transients, achieving faster transient response. With the same
modulator, the switching frequency is reduced at light load,
increasing the regulator efficiency.
The ISL62883 is fully compliant with IMVP-6.5™ specifications. It
responds to PSI# and DPRSLPVR signals by adding or dropping
PWM3 and Phase-2 respectively, adjusting overcurrent protection
threshold accordingly, and entering/exiting diode emulation mode.
It reports the regulator output current through the IMON pin. It
senses the current by using either a discrete resistor or inductor
DCR whose variation over temperature can be thermally
compensated by a single NTC thermistor. It uses differential
remote voltage sensing to accurately regulate the processor die
voltage. The adaptive body diode conduction time reduction
function minimizes the body diode conduction loss in diode
emulation mode. User-selectable overshoot reduction function
offers an option to aggressively reduce the output capacitors as
well as the option to disable it for users concerned about
increased system thermal stress. In 2-Phase configuration, the
ISL62883 offers the FB2 function to optimize 1-Phase
performance.
The ISL62883B has the same functions as the ISL62883, but
comes in a different package.
Features
• Precision Multiphase Core Voltage Regulation
- 0.5% System Accuracy Over-Temperature
- Enhanced Load Line Accuracy
• Microprocessor Voltage Identification Input
- 7-Bit VID Input, 0.300V to 1.500V in 12.5mV Steps
- Supports VID Changes On-The-Fly
• Supports Multiple Current Sensing Methods
- Lossless Inductor DCR Current Sensing
- Precision Resistor Current Sensing
• Supports PSI# and DPRSLPVR modes
• Superior Noise Immunity and Transient Response
• Current Monitor and Thermal Monitor
• Differential Remote Voltage Sensing
• High Efficiency Across Entire Load Range
• Programmable 1-, 2- or 3-Phase Operation
• Two Integrated Gate Drivers
• Excellent Dynamic Current Balance Between Phases
• FB2 Function in 2-Phase Configuration to Optimize 1-Phase
Performance
• Adaptive Body Diode Conduction Time Reduction
• User-selectable Overshoot Reduction Function
• Small Footprint 40 Ld 5x5 or 48 Ld 6x6 TQFN Package
• Pb-Free (RoHS Compliant)
Applications
• Notebook Computers
June 21, 2011
FN6891.4
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2009-2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.

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ISL62883, ISL62883B
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL62883HRTZ
62883 HRTZ
-10 to +100
40 Ld 5x5 TQFN
L40.5x5
ISL62883IRTZ
62883 IRTZ
-40 to +100
40 Ld 5x5 TQFN
L40.5x5
ISL62883BHRTZ
62883 BHRTZ
-10 to +100
48 Ld 6x6 TQFN
L48.6x6
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-
free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL62883, ISL62883B. For more information on MSL please see techbrief
TB363.
Pin Configurations
ISL62883
(40 LD TQFN)
TOP VIEW
ISL62883B
(48 LD TQFN)
TOP VIEW
40 39 38 37 36 35 34 33 32 31
PGOOD 1
PSI# 2
RBIAS 3
VR_TT# 4
NTC 5
VW 6
COMP 7
FB 8
SEN3/FB2 9
ISEN2 10
GND PAD
(BOTTOM)
30 BOOT2
29 UGATE2
28 PHASE2
27 VSSP2
26 LGATE2
25 VCCP
24 PWM3
23 LGATE1
22 VSSP1
21 PHASE1
11 12 13 14 15 16 17 18 19 20
48 47 46 45 44 43 42 41 40 39 38 37
NC 1
PGOOD 2
PSI# 3
RBIAS 4
VR_TT# 5
NTC 6
GND 7
VW 8
COMP 9
FB 10
ISEN3/FB2 11
NC 12
(BOTTOM)
36 BOOT2
35 UGATE2
34 PHASE2
33 VSSP2
32 LGATE2
31 NC
30 VCCP
29 PWM3
28 LGATE1
27 VSSP1
26 PHASE1
25 UGATE1
13 14 15 16 17 18 19 20 21 22 23 24
2 FN6891.4
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ISL62883, ISL62883B
Pin Function Descriptions
GND
Signal common of the IC. Unless otherwise stated, signals are
referenced to the GND pin.
PGOOD
Power-Good open-drain output indicating when the regulator is
able to supply regulated voltage. Pull-up externally with a 680Ω
resistor to VCCP or 1.9kΩ to 3.3V.
PSI#
Low load current indicator input. When asserted low, indicates a
reduced load-current condition. For ISL62883, when PSI# is
asserted low, PWM3 will be disabled.
RBIAS
147k resistor to GND sets internal current reference.
VR_TT#
Thermal overload output indicator.
NTC
Thermistor input to VR_TT# circuit.
VW
A resistor from this pin to COMP programs the switching
frequency (8kΩ gives approximately 300kHz).
COMP
This pin is the output of the error amplifier. Also, a resistor across
this pin and GND adjusts the overcurrent threshold.
FB
This pin is the inverting input of the error amplifier.
ISEN3/FB2
When the ISL62883 is configured in 3-phase mode, this pin is
ISEN3. ISEN3 is the individual current sensing for phase 3. When
the ISL62883 is configured in 2-phase mode, this pin is FB2.
There is a switch between the FB2 pin and the FB pin. The switch
is on in 2-phase mode and is off in 1-phase mode. The
components connecting to FB2 are used to adjust the
compensation in 1-phase mode to achieve optimum
performance.
ISEN2
Individual current sensing for Phase-2. When ISEN2 is pulled to
5V VDD, the controller will disable Phase-2 and allow other
phases to operate.
ISEN1
Individual current sensing for Phase-1.
VSEN
Remote core voltage sense input. Connect to microprocessor die.
RTN
Remote voltage sensing return. Connect to ground at
microprocessor die.
ISUM- and ISUM+
Droop current sense input.
VDD
5V bias power.
VIN
Battery supply voltage, used for feed-forward.
IMON
An analog output. IMON outputs a current proportional to the
regulator output current.
BOOT1
Connect an MLCC capacitor across the BOOT1 and the PHASE1
pins. The boot capacitor is charged through an internal boot
diode connected from the VCCP pin to the BOOT1 pin, each time
the PHASE1 pin drops below VCCP minus the voltage dropped
across the internal boot diode.
UGATE1
Output of the Phase-1 high-side MOSFET gate driver. Connect the
UGATE1 pin to the gate of the Phase-1 high-side MOSFET.
PHASE1
Current return path for the Phase-1 high-side MOSFET gate driver.
Connect the PHASE1 pin to the node consisting of the high-side
MOSFET source, the low-side MOSFET drain, and the output
inductor of Phase-1.
VSSP1
Current return path for the Phase-1 low-side MOSFET gate driver.
Connect the VSSP1 pin to the source of the Phase-1 low-side
MOSFET through a low impedance path, preferably in parallel
with the trace connecting the LGATE1 pin to the gate of the
Phase-1 low-side MOSFET.
LGATE1
Output of the Phase-1 low-side MOSFET gate driver. Connect the
LGATE1 pin to the gate of the Phase-1 low-side MOSFET.
PWM3
PWM output for Channel 3. When PWM3 is pulled to 5V VDD, the
controller will disable Phase-3 and allow other phases to operate.
VCCP
Input voltage bias for the internal gate drivers. Connect +5V to
the VCCP pin. Decouple with at least 1µF of an MLCC capacitor to
VSSP1 and VSSP2 pins respectively.
LGATE2
Output of the Phase-2 low-side MOSFET gate driver. Connect the
LGATE2 pin to the gate of the Phase-2 low-side MOSFET.
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ISL62883, ISL62883B
VSSP2
Current return path for the Phase-2 converter low-side MOSFET
gate driver. Connect the VSSP2 pin to the source of the Phase-2
low-side MOSFET through a low impedance path, preferably in
parallel with the trace connecting the LGATE2 pin to the gate of
the Phase-2 low-side MOSFET.
PHASE2
Current return path for the Phase-2 high-side MOSFET gate driver.
Connect the PHASE2 pin to the node consisting of the high-side
MOSFET source, the low-side MOSFET drain, and the output
inductor of Phase-2.
UGATE2
Output of the Phase-2 high-side MOSFET gate driver. Connect the
UGATE2 pin to the gate of the Phase-2 high-side MOSFET.
BOOT2
Connect an MLCC capacitor across the BOOT2 and the PHASE2
pins. The boot capacitor is charged through an internal boot
diode connected from the VCCP pin to the BOOT2 pin, each time
the PHASE2 pin drops below VCCP minus the voltage dropped
across the internal boot diode.
VID0, VID1, VID2, VID3, VID4, VID5, VID6
VID input with VID0 = LSB and VID6 = MSB.
VR_ON
Voltage regulator enable input. A high level logic signal on this
pin enables the regulator.
DPRSLPVR
Deeper sleep enable signal. A high level logic signal on this pin
indicates that the microprocessor is in deeper sleep mode.
CLK_EN#
Open drain output to enable system PLL clock. It goes low 13
switching cycles after Vcore is within 10% of Vboot.
NC
No Connect.
BOTTOM (on ISL62883B)
The bottom pad of ISL62883B is electrically connected to the
GND pin inside the IC.
4 FN6891.4
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Block Diagram
ISL62883, ISL62883B
VIN VSEN ISEN1 ISEN3 ISEN2 PGOOD CLK_EN#
VDD
VR_ON
PSI#
DPRSLPVR
RBIAS
VID0
VID1
VID2
VID3
VID4
VID5
VID6
RTN
FB
COMP
VW
IMON
ISUM+
ISUM-
MODE
CONTROL
DAC
AND
SOFT
START
CURRENT
BALANCE
PGOOD &
CLK_EN#
LOGIC
IBAL
PROTECTION FLT
WOC OC
VIN
CLOCK
IBAL VIN VDAC
MODULATOR
VDAC
COMP
VW
COMP
COMP
IBAL VIN VDAC
6µA 54µA 1.20V
1.24V
DRIVER
SHOOT THROUGH
PROTECTION
DRIVER
Σ
E/A
MODULATOR
COMP
IBAL VIN VDAC
IDROOP
IMON
CURRENT
SENSE
MODULATOR
2.5X
WOC
COMP
CURRENT
COMPARATORS
NUMBER OF
OC PHASES
60UA
GAIN
SELECT
Σ
DRIVER
SHOOT THROUGH
PROTECTION
DRIVER
ADJ. OCP
THRESHOLD
COMP
VR_TT#
NTC
BOOT2
UGATE2
PHASE2
LGATE2
VSSP2
PWM3
BOOT1
UGATE1
PHASE1
VCCP
LGATE1
VSSP1
GND
5 FN6891.4
June 21, 2011