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Data Sheet
ISL6324A
Hybrid SVI/PVI with I2C
March 23, 2009
FN6880.0
Monolithic Dual PWM Hybrid Controller
Powering AMD SVI Split-Plane and PVI
Uniplane Processors
The ISL6324A dual PWM controller delivers high efficiency
and tight regulation from two synchronous buck DC/DC
converters. The ISL6324A supports hybrid power control of
AMD processors which operate from either a 6-bit parallel
VID interface (PVI) or a serial VID interface (SVI). The dual
output ISL6324A features a multi-phase controller to support
uniplane VDD core voltage and a single phase controller to
power the Northbridge (VDDNB) in SVI mode. Only the
multi-phase controller is active in PVI mode to support
uniplane VDD only processors.
A precision uniplane core voltage regulation system is provided
by a 2-to-4-phase PWM voltage regulator (VR) controller. The
integration of two power MOSFET drivers, adding flexibility in
layout, reduce the number of external components in the multi-
phase section. A single phase PWM controller with integrated
driver provides a second precision voltage regulation system
for the North Bridge portion of the processor. This monolithic,
dual controller with integrated driver solution provides a cost
and space saving power management solution.
For applications which benefit from load line programming to
reduce bulk output capacitors, the ISL6324A features output
voltage droop. The multi-phase portion also includes
advanced control loop features for optimal transient response
to load application and removal. One of these features is
highly accurate, fully differential, continuous DCR current
sensing for load line programming and channel current
balance. Dual edge modulation is another unique feature,
allowing for quicker initial response to high di/dt load
transients.
The ISL6324A supports Power Savings Mode by dropping
phases when the PSI_L bit is set. The number of phases
that the ISL6324A will drop to is programmable through an
I2C interface. The number of PWM cycles between both
dropping phases when entering Power Savings Mode and
adding phases when exiting Power Savings Mode is also
programmable through the I2C interface.
The ISL6324A I2C interface also allows independent
programmable output voltage offset for both the Core and
North Bridge regulators. The I2C interface can also be used
to set the PGOOD and OVP trip levels for both regulators as
well.
Features
Processor Core Voltage Regulator Features
• Configuration Flexibility
- 2-Phase Operation with Internal Drivers
- 3- or 4-Phase Operation with External PWM Drivers
• Parallel VID (6-bit) Interface Inputs for PVI Mode
• PSI_L Support via Phase Shedding
• Differential Remote Voltage Sensing
• Optimal Processor Core Voltage Transient Response
- Adaptive Phase Alignment (APA)
- Active Pulse Positioning Modulation
Processor Core Voltage Regulator and North Bridge
Voltage Regulator Shared Features
• Precision Voltage Regulation: ±0.5% System Accuracy
Over-Temperature
• Two Wire, AMD Compliant Serial VID Interface Inputs for
SVI Mode
• I2C Interface
- Voltage Margining, OVP and PGOOD Trip Levels
- Enhanced PSI_L State Control
• Fully Differential, Continuous DCR Current Sensing
- Accurate Load Line Programming
- Precision Channel Current Balancing for Core
• Overcurrent Protection
• Multi-tiered Overvoltage Protection
• Variable Gate Drive Bias: 5V to 12V
• Simultaneous Digital Soft-Start of Both Outputs
• Selectable Switching Frequency up to 1MHz
• Pb-Free (RoHS Compliant)
Ordering Information
PART
NUMBER
(Note)
PART
MARKING
TEMP.
RANGE
(°C)
PACKAGE PKG.
(Pb-free) DWG. #
ISL6324ACRZ* ISL6324A CRZ 0 to +70 48 Ld 7x7 QFN L48.7x7
ISL6324AIRZ* ISL6324A IRZ -40 to +85 48 Ld 7x7 QFN L48.7x7
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on
reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach materials,
and 100% matte tin plate plus anneal (e3 termination finish, which is
RoHS compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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ISL6324A
ISL6324A HYBRID SVI AND PVI
(48 LD QFN)
TOP VIEW
48 47 46 45 44 43 42 41 40 39 38 37
FB_NB 1
ISEN_NB+ 2
SDA 3
VID0/VFIXEN 4
VID1/SEL 5
VID2/SVD 6
VID3/SVC 7
VID4 8
VID5 9
VCC 10
FS 11
RGND 12
49
GND
36 PWM4
35 PWM3
34 PWROK
33 PHASE1
32 UGATE1
31 BOOT1
30 LGATE1
29 PVCCI_2
28 LGATE2
27 BOOT2
26 UGATE2
25 PHASE2
13 14 15 16 17 18 19 20 21 22 23 24
Integrated Driver Block Diagram
PWM
SOFT-START
AND
FAULT LOGIC
GATE
CONTROL
LOGIC
SHOOT-
THROUGH
PROTECTION
PVCC
BOOT
UGATE
20kΩ
10kΩ
PHASE
LGATE
2 FN6880.0
March 23, 2009

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ISL6324A
www.CDaotanShtereot4llUe.cromBlock Diagram
SCL
SDA
CORE_OVP
I2C
DAC_OFS
NB_OVP
FB_NB
COMP_NB
E/A
ISEN_NB+
ISEN_NB-
CURRENT
SENSE
UV
LOGIC
OV
LOGIC
NB_REF
RAMP
MOSFET
DRIVER
VDDPWRGD
APA
COMP
FB
DVC
RGND
PWROK
VID0/VFIXEN
VID1/SEL
VID2/SVD
VID3/SVC
VID4
VID5
VSEN
RSET
ISEN1+
ISEN1-
ISEN2+
ISEN2-
ISEN3+
ISEN3-
ISEN4+
ISEN4-
APA
NB
FAULT
LOGIC
EN_12V
ENABLE
LOGIC
VDDPWRGD_MOD
E/A
2X
SOFT-START
AND
FAULT LOGIC
SVI
SLAVE
BUS
AND
PVI
DAC
DAC_OFS
LOAD APPLY
TRANSIENT
ENHANCEMENT
CLOCK AND
TRIANGLE WAVE
GENERATOR
DROOP
CONTROL
NB_REF
OV
LOGIC
UV
LOGIC
RESISTOR
MATCHING
CORE_OVP
OC
CH1
CURRENT
SENSE
CH2
CURRENT
SENSE
CH3
CURRENT
SENSE
ISEN3-
CUCRHRE4NT
SENSE
ISEN4-
I_TRIP I_AVG
CHANNEL
CURRENT
BALANCE
I_AVG 1
N
PWM1
PWM2
PWM3
PWM4
GND
POWER-ON
RESET
MOSFET
DRIVER
MOSFET
DRIVER
PH3/PH4
POR
CHANNEL
DETECT
EN_12V
ISEN3-
ISEN4-
PWM3
SIGNAL
LOGIC
PWM4
SIGNAL
LOGIC
LGATE_NB
BOOT_NB
UGATE_NB
PHASE_NB
PVCC_NB
EN
VCC
PVCC1_2
BOOT1
UGATE1
PHASE1
LGATE1
FS
BOOT2
UGATE2
PHASE2
LGATE2
PWM3
PWM4
3 FN6880.0
March 23, 2009

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www.TDaytapSihceaetl4UA.cpomplication - SVI Mode
ISL6324A
FB
COMP
ISEN3+
ISEN3-
PWM3
VSEN
BOOT1
UGATE1
PHASE1
APA
LGATE1
ISEN1-
+5V
DVC
ISEN1+
VCC
FS
PVCC1_2
BOOT2
UGATE2
PHASE2
RSET
LGATE2
VFIXEN
SEL
SVD
ISEN2-
ISEN2+
SVC
NC VID4
RGND
NC VID5
PWROK
VDDPWRGD ISEN4+
GND
ISEN4-
+12V
SCL
SDA
PWM4
ISL6324A
OFF
ON
PVCC_NB
EN
BOOT_NB
UGATE_NB
PHASE_NB
LGATE_NB
COMP_NB ISEN_NB-
FB_NB
ISEN_NB+
+12V
+12V
+12V
VDD
CPU
LOAD
+12V
+12V
BOOT1
UGATE1
PHASE1
LGATE1
PWM1
PGND
ISL6614
+12V
VCC
BOOT2 PVCC
UGATE2 GND
PHASE2
PWM2
LGATE2
VDDNB
NB
LOAD
4 FN6880.0
March 23, 2009

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www.TDaytapSihceaetl4UA.cpomplication - PVI Mode
ISL6324A
FB
COMP
ISEN3+
ISEN3-
PWM3
VSEN
BOOT1
UGATE1
PHASE1
APA
LGATE1
ISEN1-
+5V
DVC
ISEN1+
VCC
FS
PVCC1_2
BOOT2
UGATE2
PHASE2
RSET
LGATE2
VID0
VID1/SEL
VID2
ISEN2-
ISEN2+
VID3
VID4
RGND
VID5
NC PWROK
VDDPWRGD ISEN4+
GND
ISEN4-
+12V
SCL
SDA
PWM4
ISL6324A
OFF
ON
PVCC_NB
EN
BOOT_NB
UGATE_NB
PHASE_NB
LGATE_NB
COMP_NB ISEN_NB-
FB_NB
ISEN_NB+
+12V
+12V
+12V
VDD
CPU
LOAD
+12V
+12V
BOOT1
UGATE1
PHASE1
LGATE1
PWM1
PGND
ISL6614 +12V
VCC
BOOT2 PVCC
UGATE2GND
PHASE2
PWM2
LGATE2
NORTH BRIDGE REGULATOR
DISABLED IN PVI MODE
VDDNB
NB
LOAD
5 FN6880.0
March 23, 2009