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®
Data Sheet
ISL6324
Hybrid SVI/PVI with I2C
September 25, 2008
FN6518.2
Monolithic Dual PWM Hybrid Controller
Powering AMD SVI Split-Plane and PVI
Uniplane Processors
The ISL6324 dual PWM controller delivers high efficiency
and tight regulation from two synchronous buck DC/DC
converters. The ISL6324 supports hybrid power control of
AMD processors which operate from either a 6-bit parallel
VID interface (PVI) or a serial VID interface (SVI). The dual
output ISL6324 features a multiphase controller to support
uniplane VDD core voltage and a single phase controller to
power the Northbridge (VDDNB) in SVI mode. Only the
multiphase controller is active in PVI mode to support
uniplane VDD only processors.
A precision uniplane core voltage regulation system is provided
by a 2- to 4-phase PWM voltage regulator (VR) controller. The
integration of two power MOSFET drivers, adding flexibility in
layout, reduce the number of external components in the
multiphase section. A single phase PWM controller with
integrated driver provides a second precision voltage regulation
system for the North Bridge portion of the processor. This
monolithic, dual controller with integrated driver solution
provides a cost and space saving power management solution.
For applications which benefit from load line programming to
reduce bulk output capacitors, the ISL6324 features output
voltage droop. The multiphase portion also includes advanced
control loop features for optimal transient response to load
application and removal. One of these features is highly
accurate, fully differential, continuous DCR current sensing for
load line programming and channel current-balance. Dual
edge modulation is another unique feature, allowing for
quicker initial response to high di/dt load transients. The
ISL6324 incorporates an I2C bus™ that allows independent
programmable output voltage offset for both Core and
Northbridge. The I2C bus can also be used to set the
PGOOD and OVP levels.
Ordering Information
PART
NUMBER
(Note)
PART
MARKING
TEMP.
(°C)
PACKAGE PKG.
(Pb-free) DWG. #
ISL6324CRZ* ISL6324 CRZ 0 to +70 48 Ld 7x7 QFN L48.7x7
ISL6324IRZ* ISL6324 IRZ -40 to +85 48 Ld 7x7 QFN L48.7x7
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on
reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
Features
• Processor Core Voltage Via Integrated Multiphase Power
Conversion
• Configuration Flexibility
- 2-Phase Operation with Internal Drivers
- 3- or 4-Phase Operation with External PWM Drivers
• Serial VID Interface Inputs
- Two Wire, Clock and Data, Bus
- Conforms to AMD SVI Specifications
• Parallel VID Interface Inputs
- 6-bit VID input
- 0.775V to 1.55V in 25mV Steps
- 0.375V to 0.7625V in 12.5mV Steps
• Precision Core Voltage Regulation
- Differential Remote Voltage Sensing
- ±0.5% System Accuracy Over-Temperature
- Adjustable Reference-Voltage Offset
• Optimal Processor Core Voltage Transient Response
- Adaptive Phase Alignment (APA)
- Active Pulse Positioning Modulation
• I2C bus for Voltage Margining Offset
• Fully Differential, Continuous DCR Current Sensing
- Accurate Load Line Programming
- Precision Channel Current Balancing
• Variable Gate Drive Bias: 5V to 12V
• Overcurrent Protection
• Multi-tiered Overvoltage Protection
• Selectable Switching Frequency up to 1MHz
• Simultaneous Digital Soft-Start of Both Outputs
• Processor NorthBridge Voltage Via Single Phase Power
Conversion
• Precision Voltage Regulation
- Differential Remote Voltage Sensing
- ±0.5% System Accuracy Over-Temperature
• I2Cbus for Voltage Margining Offset
• Serial VID Interface Inputs
- Two Wire, Clock and Data, Bus
- Conforms to AMD SVI Specifications
• Overcurrent Protection
• Continuous DCR Current Sensing
• Variable Gate Drive Bias: 5V to 12V
• Simultaneous Digital Soft-Start of Both Outputs
• Selectable Switching Frequency up to 1MHz
• Pb-Free (RoHS Compliant)
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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ISL6324
ISL6324 HYBRID SVI AND PVI
(48 LD QFN)
TOP VIEW
48 47 46 45 44 43 42 41 40 39 38 37
FB_NB 1
ISEN_NB+ 2
SDA 3
VID0/VFIXEN 4
VID1/SEL 5
VID2/SVD 6
VID3/SVC 7
VID4 8
VID5 9
VCC 10
FS 11
RGND 12
49
GND
36 PWM4
35 PWM3
34 PWROK
33 PHASE1
32 UGATE1
31 BOOT1
30 LGATE1
29 PVCCI_2
28 LGATE2
27 BOOT2
26 UGATE2
25 PHASE2
13 14 15 16 17 18 19 20 21 22 23 24
Integrated Driver Block Diagram
PWM
SOFT-START
AND
FAULT LOGIC
GATE
CONTROL
LOGIC
SHOOT-
THROUGH
PROTECTION
PVCC
BOOT
UGATE
20kΩ
10kΩ
PHASE
LGATE
2 FN6518.2
September 25, 2008

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ISL6324
www.CDaotanShtereot4llUe.cromBlock Diagram
SCL
SDA
CORE_OVP
I2C
DAC_OFS
NB_OVP
FB_NB
COMP_NB
E/A
ISEN_NB+
ISEN_NB-
VDDPWRGD
APA
COMP
FB
DVC
CURRENT
SENSE
UV
LOGIC
OV
LOGIC
NB_REF
NB_CS
APA
VDDPWRGD_MOD
E/A
2X
NB
FAULT
LOGIC
SOFT-START
AND
FAULT LOGIC
RAMP
EN_12V
ENABLE
LOGIC
MOSFET
DRIVER
POWER-ON
RESET
RGND
PWROK
VID0/VFIXEN
VID1/SEL
VID2/SVD
VID3/SVC
VID4
VID5
VSEN
RSET
ISEN1+
ISEN1-
ISEN2+
ISEN2-
ISEN3+
ISEN3-
ISEN4+
ISEN4-
SVI
SLAVE
BUS
AND
PVI
DAC
DAC_OFS
LOAD APPLY
TRANSIENT
ENHANCEMENT
CLOCK AND
TRIANGLE WAVE
GENERATOR
DROOP
CONTROL
NB_REF
OV
LOGIC
UV
LOGIC
RESISTOR
MATCHING
CORE_OVP
NB_CS
OC
CH1
CURRENT
SENSE
CH2
CURRENT
SENSE
CH3
CURRENT
SENSE
ISEN3-
CUCRHRE4NT
SENSE
ISEN4-
I_TRIP I_AVG
CHANNEL
CURRENT
BALANCE
I_AVG 1
N
PWM1
PWM2
PWM3
PWM4
GND
MOSFET
DRIVER
MOSFET
DRIVER
PH3/PH4
POR
CHANNEL
DETECT
EN_12V
ISEN3-
ISEN4-
PWM3
SIGNAL
LOGIC
PWM4
SIGNAL
LOGIC
LGATE_NB
BOOT_NB
UGATE_NB
PHASE_NB
PVCC_NB
EN
VCC
PVCC1_2
BOOT1
UGATE1
PHASE1
LGATE1
FS
BOOT2
UGATE2
PHASE2
LGATE2
PWM3
PWM4
3 FN6518.2
September 25, 2008

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www.TDaytapSihceaetl4UA.cpomplication - SVI Mode
ISL6324
FB
COMP
ISEN3+
ISEN3-
PWM3
VSEN
BOOT1
UGATE1
PHASE1
APA
LGATE1
ISEN1-
+5V
DVC
ISEN1+
VCC
FS
PVCC1_2
BOOT2
UGATE2
PHASE2
RSET
LGATE2
VFIXEN
SEL
SVD
ISEN2-
ISEN2+
SVC
NC VID4
RGND
NC VID5
PWROK
VDDPWRGD ISEN4+
GND
ISEN4-
+12V
SCL
SDA
PWM4
ISL6324
OFF
ON
PVCC_NB
EN
BOOT_NB
UGATE_NB
PHASE_NB
LGATE_NB
COMP_NB ISEN_NB-
FB_NB
ISEN_NB+
+12V
+12V
+12V
VDD
CPU
LOAD
+12V
+12V
BOOT1
UGATE1
PHASE1
LGATE1
PWM1
PGND
ISL6614 +12V
VCC
BOOT2 PVCC
UGATE2 GND
PHASE2
PWM2
LGATE2
VDDNB
NB
LOAD
4 FN6518.2
September 25, 2008

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www.TDaytapSihceaetl4UA.cpomplication - PVI Mode
ISL6324
FB
COMP
ISEN3+
ISEN3-
PWM3
VSEN
BOOT1
UGATE1
PHASE1
APA
LGATE1
ISEN1-
+5V
DVC
ISEN1+
VCC
FS
PVCC1_2
BOOT2
UGATE2
PHASE2
RSET
LGATE2
VID0
VID1/SEL
VID2
ISEN2-
ISEN2+
VID3
VID4
RGND
VID5
NC PWROK
VDDPWRGD ISEN4+
GND
ISEN4-
+12V
SCL
SDA
PWM4
ISL6324
OFF
ON
PVCC_NB
EN
BOOT_NB
UGATE_NB
PHASE_NB
LGATE_NB
COMP_NB ISEN_NB-
FB_NB
ISEN_NB+
+12V
+12V
+12V
VDD
CPU
LOAD
+12V
+12V
BOOT1
UGATE1
PHASE1
LGATE1
PWM1
PGND
ISL6614 +12V
VCC
BOOT2 PVCC
UGATE2 GND
PHASE2
PWM2
LGATE2
NORTH BRIDGE REGULATOR
DISABLED IN PVI MODE
VDDNB
NB
LOAD
5 FN6518.2
September 25, 2008