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®
Data Sheet
March 23, 2009
ISL6323B
FN6879.0
Monolithic Dual PWM Hybrid Controller
Powering AMD SVI Split-Plane and PVI
Uniplane Processors
The ISL6323B dual PWM controller delivers high efficiency
and tight regulation from two synchronous buck DC/DC
converters. The ISL6323B supports hybrid power control of
AMD processors which operate from either a 6-bit parallel
VID interface (PVI) or a serial VID interface (SVI). The dual
output ISL6323B features a multi-phase controller to support
uniplane VDD core voltage and a single phase controller to
power the Northbridge (VDDNB) in SVI mode. Only the
multi-phase controller is active in PVI mode to support
uniplane VDD only processors.
A precision uniplane core voltage regulation system is
provided by a two-to-four-phase PWM voltage regulator (VR)
controller. The integration of two power MOSFET drivers,
adding flexibility in layout, reduce the number of external
components in the multi-phase section. A single phase PWM
controller with integrated driver provides a second precision
voltage regulation system for the North Bridge portion of the
processor. This monolithic, dual controller with integrated
driver solution provides a cost and space saving power
management solution.
For applications which benefit from load line programming to
reduce bulk output capacitors, the ISL6323B features output
voltage droop. The multi-phase portion also includes
advanced control loop features for optimal transient
response to load apply and removal. One of these features
is highly accurate, fully differential, continuous DCR current
sensing for load line programming and channel current
balance. Dual edge modulation is another unique feature,
allowing for quicker initial response to high di/dt load
transients.
The ISL6323B supports Power Savings Mode by dropping
the number of phases to two when the PSI_L bit is set.
Ordering Information
PART NUMBER
(Note)
PART
MARKING
TEMP.
RANGE
(°C)
PACKAGE PKG.
(Pb-free) DWG. #
ISL6323BCRZ* ISL6323B CRZ 0 to +70 48 Ld 7x7 QFN L48.7x7
ISL6323BIRZ* ISL6323B IRZ -40 to +85 48 Ld 7x7 QFN L48.7x7
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel
specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Features
• Processor Core Voltage Via Integrated Multi-Phase
Power Conversion
• Configuration Flexibility
- 2-Phase Operation with Internal Drivers
- 3- or 4-Phase Operation with External PWM Drivers
• PSI_L Support with Phase Shedding for Improved
Efficiency at Light Load
• Serial VID Interface Inputs
- Two Wire, Clock and Data, Bus
- Conforms to AMD SVI Specifications
• Parallel VID Interface Inputs
- 6-bit VID input
- 0.775V to 1.55V in 25mV Steps
- 0.375V to 0.7625V in 12.5mV Steps
• Precision Core Voltage Regulation
- Differential Remote Voltage Sensing
- ±0.6% System Accuracy Over-Temperature
- Adjustable Reference-Voltage Offset
• Optimal Processor Core Voltage Transient Response
- Adaptive Phase Alignment (APA)
- Active Pulse Positioning Modulation
• Fully Differential, Continuous DCR Current Sensing
- Accurate Load Line Programming
- Precision Channel Current Balancing
• Variable Gate Drive Bias: 5V to 12V
• Overcurrent Protection
• Multi-tiered Overvoltage Protection
• Selectable Switching Frequency up to 1MHz
• Simultaneous Digital Soft-Start of Both Outputs
• Processor NorthBridge Voltage Via Single Phase
Power Conversion
• Precision Voltage Regulation
- Differential Remote Voltage Sensing
- ±0.6% System Accuracy Over Temperature
• Serial VID Interface Inputs
- Two Wire, Clock and Data, Bus
- Conforms to AMD SVI Specifications
• Overcurrent Protection
• Continuous DCR Current Sensing
• Variable Gate Drive Bias: 5V to 12V
• Simultaneous Digital Soft-Start of Both Outputs
• Selectable Switching Frequency up to 1MHz
• Pb-Free (RoHS Compliant)
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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ISL6323B
ISL6323B
(48 LD QFN)
TOP VIEW
48 47 46 45 44 43 42 41 40 39 38 37
FB_NB 1
36 PWM4
ISEN_NB+ 2
35 PWM3
RGND_NB 3
34 PWROK
VID0/VFIXEN 4
33 PHASE1
VID1/SEL 5
32 UGATE1
VID2/SVD 6
VID3/SVC 7
49
GND
31 BOOT1
30 LGATE1
VID4 8
29 PVCC1_2
VID5 9
28 LGATE2
VCC 10
27 BOOT2
FS 11
RGND 12
26 UGATE2
25 PHASE2
13 14 15 16 17 18 19 20 21 22 23 24
Integrated Driver Block Diagram
PWM
SOFT-START
AND
FAULT LOGIC
GATE
CONTROL
LOGIC
SHOOT-
THROUGH
PROTECTION
PVCC
BOOT
UGATE
20KΩ
10KΩ
PHASE
LGATE
2 FN6879.0
March 23, 2009

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ISL6323B
www.CDaotanShtereot4llUe.cromBlock Diagram
RGND_NB
FB_NB
COMP_NB
ISEN_NB+
ISEN_NB-
VDDPWRGD
APA
COMP
OFS
FB
DVC
RGND
PWROK
VID0/VFIXEN
VID1/SEL
VID2/SVD
VID3/SVC
VID4
VID5
VSEN
RSET
ISEN1+
ISEN1-
ISEN2+
ISEN2-
ISEN3+
ISEN3-
ISEN4+
ISEN4-
NB_REF
CURRENT
SENSE
UV
LOGIC
OV
LOGIC
E/A
RAMP
MOSFET
DRIVER
APA
OFFSET
2X
E/A
SVI
SLAVE
BUS
AND
PVI
DAC
NB
FAULT
LOGIC
SOFT-START
AND
FAULT LOGIC
EN_12V
ENABLE
LOGIC
POWER-ON
RESET
LOAD APPLY
TRANSIENT
ENHANCEMENT
CLOCK AND
TRIANGLE WAVE
GENERATOR
DROOP
CONTROL
MOSFET
DRIVER
NB_REF
OV
LOGIC
UV
LOGIC
RESISTOR
MATCHING
CH1
CURRENT
SENSE
OC
I_TRIP I_AVG
PWM1
PWM2
PWM3
PWM4
CH2
CURRENT
SENSE
CH3
CURRENT
SENSE
ISEN3-
CH4
CURRENT
SENSE
ISEN4-
CHANNEL
CURRENT
BALANCE
I_AVG
1
N
GND
MOSFET
DRIVER
PH3/PH4
POR
CHANNEL
DETECT
EN_12V
ISEN3-
ISEN4-
PWM3
SIGNAL
LOGIC
PWM4
SIGNAL
LOGIC
BOOT_NB
UGATE_NB
PHASE_NB
LGATE_NB
PVCC_NB
EN
VCC
PVCC1_2
BOOT1
UGATE1
PHASE1
LGATE1
FS
BOOT2
UGATE2
PHASE2
LGATE2
PWM3
PWM4
3 FN6879.0
March 23, 2009

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www.TDaytapSihceaetl4UA.cpomplication - SVI Mode
ISL6323B
FB
COMP
ISEN3+
ISEN3-
PWM3
VSEN
BOOT1
UGATE1
PHASE1
APA
DVC
LGATE1
ISEN1-
ISEN1+
+5V
+5V
VCC
OFS
FS
PVCC1_2
BOOT2
UGATE2
PHASE2
RSET
LGATE2
VFIXEN
SEL
SVD
ISEN2-
ISEN2+
SVC
NC VID4
RGND
NC VID5
PWROK
VDDPWRGD ISEN4+
GND
ISEN4-
+12V
PWM4
ISL6323B
OFF
ON
PVCC_NB
EN
BOOT_NB
UGATE_NB
PHASE_NB
LGATE_NB
COMP_NB ISEN_NB-
FB_NB
ISEN_NB+
+12V
+12V
+12V
VDD
CPU
LOAD
+12V
+12V
BOOT1
UGATE1
PHASE1
LGATE1
PWM1
PGND
ISL6614
+12V
VCC
BOOT2 PVCC
UGATE2 GND
PHASE2
PWM2
LGATE2
VDDNB
NB
LOAD
4 FN6879.0
March 23, 2009

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www.TDaytapSihceaetl4UA.cpomplication - PVI Mode
ISL6323B
FB
COMP
ISEN3+
ISEN3-
PWM3
VSEN
BOOT1
UGATE1
PHASE1
APA
DVC
LGATE1
ISEN1-
ISEN1+
+5V
+5V
VCC
OFS
FS
PVCC1_2
BOOT2
UGATE2
PHASE2
RSET
LGATE2
VID0
VID1/SEL
VID2
ISEN2-
ISEN2+
VID3
VID4
RGND
VID5
NC PWROK
VDDPWRGD ISEN4+
GND
ISEN4-
+12V
PWM4
ISL6323B
OFF
ON
PVCC_NB
EN
BOOT_NB
UGATE_NB
PHASE_NB
LGATE_NB
COMP_NB ISEN_NB-
FB_NB
ISEN_NB+
+12V
+12V
+12V
VDD
CPU
LOAD
+12V
+12V
BOOT1
UGATE1
PHASE1
LGATE1
PWM1
PGND
ISL6614 +12V
VCC
BOOT2 PVCC
UGATE2GND
PHASE2
PWM2
LGATE2
NORTH BRIDGE REGULATOR
DISABLED IN PVI MODE
VDDNB
NB
LOAD
5 FN6879.0
March 23, 2009