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® ST9040
16K ROM HCMOS MCU
WITH EEPROM, RAM AND A/D CONVERTER
Register oriented 8/16 bit CORE with
RUN, WFI and HALT modes
Minimum instruction cycle time : 500ns
(12MHz internal)
Internal Memory :
ROM
16K bytes
RAM
256 bytes
EEPROM
512 bytes
224 general purpose registers available as RAM,
accumulators or index registers (register file)
80-pin PQFP package for ST9040Q
68-lead PLCC package for ST9040C
DMA controller, Interrupt handler and Serial Pe-
ripheral Interface as standard features
Up to 56 fully programmable I/O pins
Up to 8 external plus 1 non-maskableinterrupts
16 bit Timer with 8 bit Prescaler, able to be used
as a WatchdogTimer
Two 16 bit Multifunction Timers, each with an 8
bit prescaler and 13 operating modes
8 channel 8 bit Analog to Digital Converter, with
Analog Watchdogs and external references
Serial Communications Interface with asynchro-
nous and synchronous capability
Rich Instruction Set and 14 Addressingmodes
Division-by-Zero trap generation
Versatile developmenttools, including assembler,
linker, C-compiler, archiver, graphic oriented de-
buggerand hardware emulators
Real Time Operating System
Windowed and One Time Programmable EPROM
parts available for prototyping and pre-production
development phases
Pin to pin compatible with ST9036
PQFP80
PLCC68
(Ordering Information at the end of the Datasheet)
February 1997
1/56

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TABLE OF CONTENTS
ST9040 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.1 I/O Port Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.2 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.2.2 EEPROM Programming Procedure . . . . . . . . . . . . . . . . . .
1.3.2.3 Parallel Programming Procedure . . . . . . . . . . . . . . . . . . .
1.3.2.4 EEPROM Programming Voltage . . . . . . . . . . . . . . . . . . .
1.3.2.5 EEPROM Programming Time . . . . . . . . . . . . . . . . . . . . .
1.3.2.6 EEPROM Interrupt Management . . . . . . . . . . . . . . . . . . .
1.3.2.7 EEPROM Control Register . . . . . . . . . . . . . . . . . . . . . .
1.3.3 REGISTER MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
5
6
6
10
10
10
10
11
11
11
11
11
12
12
2 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
ST90E40 / ST90T40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.1 I/O PORT ALTERNATE FUNCTIONS . . . . . . . . . . . . . . . . . . . .
1.1 MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 EPROM PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.1 Eprom Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ST90R40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.1 I/O PORT ALTERNATE FUNCTIONS . . . . . . . . . . . . . . . . . . . .
1.3 MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
38
39
39
42
42
42
49
51
52
52
55
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Figure 1. 80 Pin PQFP Package
ST9040
Table 1. ST9040Q Pin Description
Pin Name
1 AVSS
2 NC
3 NC
4 P44/AIN4
5 P57
6 P56
7 P55
8 P54
9 INT7
10 INT0
11 P53
12 NC
13 P52
14 P51
15 P50
16 OSCOUT
17 VSS
18 VSS
19 NC
20 OSCIN
21 RESET
22 P37/T1OUTB
23 P36/T1INB
24 P35/T1OUTA
Pin Name
25 P34/T1INA
26 P33/T0OUTB
27 P32/T0INB
28 P31/T0OUTA
29 P30/P/D/T0INA
30 A15
31 A14
32 NC
33 A13
34 A12
35 A11
36 A10
37 A9
38 A8
39 P00/A0/D0
40 P01/A1/D1
®
Pin Name
64 P20/NMI
63 NC
62 VSS
61 P70/SIN
60 P71/SOUT
59
P72/INT4/TXCLK
/CLKOUT
58
P73/INT5
/RXCLK/ADTRG
57 P74/P/D/INT6
56 P75/WAIT
55
P76/WDOUT
/BUSREQ
54
P77/WDIN
/BUSACK
53 R/W
52 NC
51 DS
50 AS
49 NC
48 VDD
47 VDD
46 P07/A7/D7
45 P06/A6/D6
44 P05/A5/D5
43 P04/A4/D4
42 P03/A3/D3
41 P02/A2/D2
Pin Name
80 AVDD
79 NC
78 P47/AIN7
77 P46/AIN6
76 P45/AIN5
75 P43/AIN3
74 P42/AIN2
73 P41/AIN1
72 P40/AIN0
71 P27/RRDY5
70
P26/INT3
/RDSTB5/P/D
69 P25/WRRDY5
68
P24/INT1
/WRSTB5
67 P23/SDO
66 P22/INT2/SCK
65 P21/SDI/P/D
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ST9040
Figure 2. 68 Pin PLCC Package
Table 2. ST9040C Pin Description
Pin
61
62
63
64
65
66
67
68
q1
2
3
4
5
6
7
8
9
Name
P44/AIN4
P57
P56
P55
P54
INT7
INT0
P53
P52
P51
P50
OSCOUT
VSS
OSCIN
RESET
P37/T1OUTB
P36/T1INB
Pin Name
10 P35/T1OUTA
11 P34/T1INA
12 P33/T0OUTB
13 P32/T0INB
14 P31/T0OUTA
15 P30/P/D/T0INA
16 P17/A15
17 P16/A14
18 P15/A13
19 P14/A12
20 P13/A11
21 P12/A10
22 P11/A9
23 P10/A8
24 P00/A0/D0
25 P01/A1/D1
26 P02/A2/D2
Pin Name
43 P70/SIN
42 P71/SOUT
41
P72/CLKOUT
/TXCLK/INT4
40
P73/ADTRG
/RXCLK/INT5
39 P74/P/D/INT6
38 P75/WAIT
37
P76/WDOUT
/BUSREQ
36
P77/WDIN
/BUSACK
35 R/W
34 DS
33 AS
32 VDD
31 P07/A7/D7
30 P06/A6/D6
29 P05/A5/D5
28 P04/A4/D4
27 P03/A3/D3
Pin Name
60 AVSS
59 AVDD
58 P47/AIN7
57 P46/AIN6
56 P45/AIN5
55 P43/AIN3
54 P42/AIN2
53 P41/AIN1
52 P40/AIN0
51 P27/RRDY5
50
P26/INT3
/RDSTB5/P/D
49 P25/WRRDY5
48
P24/INT1
/WRSTB5
47 P23/SDO
46 P22/INT2/SCK
45 P21/SDI/P/D
44 P20/NMI
4/56
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ST9040
1.1GENERAL DESCRIPTION
The ST9040 is a ROM member of the ST9 family of
microcontrollers, completely developed and pro-
duced by SGS-THOMSON Microelectronics using
a proprietary n-well HCMOS process.
The ST9040 peripheral and functional actions are
fully compatible throughout the ST903x/4x family.
This datasheet will thus provide only information
specific to this ROM device.
THE READER IS ASKED TO REFER TO THE
DATASHEET OF THE ST9036 ROM-BASED DE-
VICE FOR FURTHER DETAILS.
The nucleus of the ST9040 is the advanced Core
which includes the Central Processing Unit (CPU),
the Register File, a 16 bit Timer/Watchdog with 8
bit Prescaler, a Serial Peripheral Interface support-
ing S-bus, I2C-bus and IM-bus Interface,plus two 8
bit I/O ports. The Core has independent memory
and register buses allowing a high degree of pipe-
lining to add to the efficiency of the code execution
speed of the extensive instruction set. The power-
ful I/O capabilities demanded by microcontroller
applications are fulfilled by the ST9040 with up to
56 I/O lines dedicated to digital Input/Output.
These lines are grouped into up to seven 8 bit I/O
Ports and can be configured on a bit basis under
software control to provide timing, status signals,
an address/databus for interfacing external mem-
ory, timer inputs and outputs, analog inputs, exter-
nal interrupts and serial or parallel I/O with or
without handshake.
Three basic memory spaces are available to support
this wide range of configurations: Program Memory
(internaland external), Data Memory (internaland ex-
ternal)andtheRegisterFile, which includesthecontrol
andstatus registers of theon-chip peripherals.
Two 16 bit MultiFunction Timers, each with an 8 bit
Prescaler and 13 operating modes allow simple
use for complex waveform generation and meas-
urement, PWM functions and many other system
timing functionsby the usage of the two associated
DMA channels for each timer. In addition there is
an 8 channel Analog to Digital Converter with inte-
gral sample and hold, fast 11µs conversion time
and 8 bit resolution. An Analog Watchdog feature
is included for two input channels.
Completing the device is a full duplex Serial Com-
munications Interface with an integral 110 to
375,000 baud rate generator, asynchronous and
1.5Mbyte/s synchronous capability (fully program-
mable format) and associated address/wake-up
option, plus two DMA channels.
5/56
®