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Preliminary
.
IBM0418A81BLAB IBM0436A81BLAB
IBM0418A41BLAB IBM0436A41BLAB
8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
Features
• 8Mb: 256K x 36 or 512K x 18 organizations
4Mb: 128K x 36 or 256K x 18 organizations
• 0.25 Micron CMOS technology
• Synchronous Pipeline Mode of Operation with
Self-Timed Late Write
• Single Differential HSTL Clock
• +2.5V Power Supply, Ground, 1.5, 1.8V VDDQ,
and 0.90V VREF
• HSTL Input and Output levels
• Registered Addresses, Write Enables, Synchro-
nous Select, and Data Ins
• Registered Outputs
• Common I/O
• Asynchronous Output Enable
• Synchronous Power Down Input
• Boundary Scan using limited set of JTAG
1149.1 functions
• Byte Write Capability and Global Write Enable
• 7 x 17 Bump Ball Grid Array Package with
SRAM JEDEC Standard Pinout and Boundary
SCAN Order
Description
The 4Mb and 8Mb SRAMs—IBM0436A41BLAB,
IBM0418A41BLAB, IBM0418A81BLAB, and
IBM0436A81BLAB—are Synchronous Pipeline
Mode, high-performance CMOS Static Random
Access Memories that are versatile, wide I/O, and
can achieve 3ns cycle times. Differential K clocks
are used to initiate the read/write operation and all
internal operations are self-timed. At the rising edge
of the K clock, all Addresses, Write-Enables, Sync
Select, and Data Ins are registered internally. Data
Outs are updated from output registers off the next
rising edge of the K clock. An internal Write buffer
allows write data to follow one cycle after addresses
and controls. The device is operated with a single
+2.5V power supply and is compatible with HSTL
I/O interfaces.
crrh2519.07
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Use is further subject to the provisions at the end of this document.
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IBM0418A81BLAB IBM0436A81BLAB
www.DatIaBSMhe0e4t14U8A.c4o1mBLAB IBM0436A41BLAB
8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
Preliminary
x36 BGA Pinout (Top View)
1234567
A VDDQ
SA
SA
NC
SA
SA VDDQ
B NC NC SA NC SA NC, SA(8Mb) NC
C NC SA SA VDD SA SA NC
D DQ23
DQ19
VSS
ZQ
VSS
DQ10
DQb9
E DQ20
DQ26
VSS
SS
VSS
DQ12
DQb11
F VDDQ
DQ22
VSS
G
VSS
DQ13
VDDQ
G DQ18
DQ24
SBWc
NC
SBWb
DQ15
DQb14
H DQ25
DQ21
VSS
NC
VSS
DQ17
DQb16
J VDDQ
VDD
VREF
VDD
VREF
VDD
VDDQ
K DQ34
DQ35
VSS
K
VSS
DQ8
DQ7
L DQ32
DQ33
SBWd
K
SBWa
DQ6
DQ5
M VDDQ
DQ31
VSS
SW
VSS
DQ4
VDDQ
N DQ29
DQ30
VSS
SA0
VSS
DQ3
DQ2
P DQ27
DQ28
VSS
SA1
VSS
DQ1
DQ0
R NC
SA
M1* VDD M2*
SA
NC
T NC NC SA SA SA NC ZZ
U VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Note: * M1 and M2 are clock mode pins. For this application, M1 and M2 need to connect to VSS and VDD, respectively.
x18 BGA Pinout (Top View)
1234567
A VDDQ
SA
SA
NC
SA
SA VDDQ
B NC NC SA NC SA NC, SA(8Mb) NC
C NC SA SA VDD SA SA NC
D DQ9
NC
VSS
ZQ
VSS DQ1 NC
E NC
DQ15
VSS
SS
VSS
NC DQ4
F VDDQ
NC
VSS
G
VSS
DQ5
VDDQ
G NC
DQ16
SBWb
NC
NC
NC DQ8
H DQ12
NC
VSS
NC
VSS DQ2
NC
J VDDQ
VDD
VREF
VDD
VREF
VDD
VDDQ
K NC
DQ11
VSS
K
VSS NC DQ3
L DQ13
NC
NC
K
SBWa
DQ7
NC
M VDDQ
DQ17
VSS
SW
VSS
NC VDDQ
N DQ14
NC
VSS SA0 VSS DQ0
NC
P NC
DQ10
VSS
SA1
VSS
NC
DQ6
R NC SA M1 VDD M2 SA NC
T NC SA SA NC SA SA ZZ
U VDDQ
TMS
TDI
TCK
TDO
NC VDDQ
Note: * M1 and M2 are clock mode pins. For this application, M1 and M2 need to connect to VSS and VDD respectively.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
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Preliminary
IBM0418A81BLAB IBM0436A81BLAB
IBM0418A41BLAB IBM0436A41BLAB
8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
Pin Description
SA0-SA18
DQ0-DQ35
Address Input
SA0-SA18 for 512K x 18
SA0-SA17 for 256K x 36
SA0-SA17 for 256K x 18
SA0-SA16 for 128K x 36
Data I/O
DQ0-DQ17 for 512K x 18
DQ0-DQ35 for 256K x 36
K, K Differential Input Register Clocks
SW
SBWa
SBWb
SBWc
SBWd
TMS,TDI,TCK
TDO
Write Enable, Global
Write Enable, Byte a (DQ0-DQ8)
Write Enable, Byte b (DQ9-DQ17)
Write Enable, Byte c (DQ18-DQ26)
Write Enable, Byte d (DQ27-DQ35)
IEEE 1149.1 Test Inputs (LVTTL levels)
IEEE 1149.1 Test Output (LVTTL level)
G Asynchronous Output Enable
SS Synchronous Select
M1, M2
VREF(2)
VDD
VSS
VDDQ
ZZ
ZQ
NC
Clock Mode Inputs - Selects Single or Dual
Clock Operation.
HSTL Input Reference Voltage
Power Supply (+2.5V)
Ground
Output Power Supply
Synchronous Sleep Mode
Output Driver Impedance Control
No Connect
Ordering Information (These are all possible sorts; some may not be qualified.)
Part Number
IBM0418A41BLAB - 3
IBM0418A41BLAB - 3F
IBM0418A41BLAB - 3N
IBM0418A41BLAB - 4
IBM0418A41BLAB - 5
IBM0436A41BLAB - 3
IBM0436A41BLAB - 3F
IBM0436A41BLAB - 3N
IBM0436A41BLAB - 4
IBM0436A41BLAB - 5
IBM0418A81BLAB - 3
IBM0418A81BLAB - 3F
IBM0418A81BLAB - 3N
IBM0418A81BLAB - 4
IBM0418A81BLAB - 5
IBM0436A81BLAB -3
IBM0436A81BLAB -3F
IBM0436A81BLAB - 3N
IBM0436A81BLAB -4
IBM0436A81BLAB -5
Organization
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
128K x 36
128K x 36
128K x 36
128K x 36
128K x 36
512K x 18
512K x 18
512K x 18
512K x 18
512K x 18
256K x 36
256K x 36
256K x 36
256K x 36
256K x 36
Speed
1.7ns Access / 3.0ns Cycle
1.8ns Access / 3.3ns Cycle
1.8ns Access / 3.7ns Cycle
2.0ns Access / 4.0ns Cycle
2.25ns Access /5.0ns Cycle
1.7ns Access / 3.0ns Cycle
2.0ns Access / 3.3ns Cycle
1.8ns Access / 3.7ns Cycle
2.0ns Access / 4.0ns Cycle
2.25ns Access /5.0ns Cycle
1.7ns Access / 3.0ns Cycle
1.8ns Access / 3.3ns Cycle
1.8ns Access / 3.7ns Cycle
2.0ns Access / 4.0ns Cycle
2.25ns Access /5.0ns Cycle
1.7ns Access / 3.0ns Cycle
1.8ns Access / 3.3ns Cycle
1.8ns Access / 3.7ns Cycle
2.0ns Access / 4.0ns Cycle
2.25ns Access /5.0ns Cycle
Leads
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
crrh2519.07
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©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
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IBM0418A81BLAB IBM0436A81BLAB
www.DatIaBSMhe0e4t14U8A.c4o1mBLAB IBM0436A41BLAB
8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
Block Diagram
SBW
Preliminary
SA0-SA18
K
SS
LATCH
ZZ
SW
LATCH0
G
DOC_MUX0
DOC_Array0
Col Decode
Read/Wr Amp
SW0
REG
SW1
REG
SS0
REG
SS1
REG
DOC_MUX2
2:1 MUX
DOC_MUX1
2:1 MUX
DOC_
DOUT0
DQ0-DQ35
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
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Preliminary
IBM0418A81BLAB IBM0436A81BLAB
IBM0418A41BLAB IBM0436A41BLAB
8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
SRAM Features
Late Write
Late Write function allows for write data to be registered one cycle after addresses and controls. This feature
eliminates one bus-turnaround cycle, necessary when going from a Read to a Write operation. Late Write is
accomplished by buffering write addresses and data so that the write operation occurs during the next write
cycle. When a read cycle occurs after a write cycle, the address and write data information are stored tempo-
rarily in holding registers. During the first write cycle preceded by a read cycle, the SRAM array will be
updated with address and data from the holding registers. Read cycle addresses are monitored to determine
if read data is to be supplied from the SRAM array or the write buffer. The bypassing of the SRAM array
occurs on a byte-by-byte basis. When only one byte is written during a write cycle, read data from the last
written address will have new byte data from the write buffer and remaining bytes from the SRAM array.
Mode Control
Mode control pins M1 and M2 are used to select four different JEDEC-standard read protocols. This SRAM
supports Single Clock, Pipeline (M1 = VSS, M2 = VDD). This datasheet only describes Single Clock Pipeline
functionality. Mode control inputs must be set with power up and must not change during SRAM operation.
This SRAM is tested only in the Pipeline mode.
Sleep Mode
Sleep Mode is enabled by switching synchronous signal ZZ High. When the SRAM is in Sleep mode, the out-
puts will go to a High-Z state and the SRAM will draw standby current. SRAM data will be preserved and a
recovery time (tZZR) is required before the SRAM resumes normal operation.
RQ Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow for the
SRAM to adjust its output driver impedance. The value of RQ must be tbdX the value of the intended line
impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching is between
175and 350, with the tolerance described in Programmable Impedance Output Driver DC Electrical Char-
acteristics on page 9. The RQ resistor should be placed less than two inches away from the ZQ ball on the
SRAM module. The total external capacitance (including wiring ) seen by the ZQ ball should be minimized
(less than 7.5 pF).
Programmable Impedance and Power-Up Requirements
Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by
drifts in supply voltage and temperature. One evaluation occurs every 64 clock cycles and each evaluation
may move the output driver impedance level only one step at a time towards the optimum level. The output
driver has 32 discrete binary weighted steps. The impedance update of the output driver occurs when the
SRAM is in High-Z. Write and Deselect operations will synchronously switch the SRAM into and out of High-
Z, therefore triggering an update. The user may choose to invoke asynchronous G updates by providing a G
setup and hold about the K clock to guarantee the proper update. There are no power-up requirements for
the SRAM; however, to guarantee optimum output driver impedance after power up, the SRAM needs 4096
clock cycles followed by a Low-Z to High-Z transition.
Power-Up and Power-Down Sequencing
The Power supplies need to be powered up in the following order: VDD, VDDQ, VREF, and Inputs. The power-
down sequencing must be the reverse. VDDQ can be allowed to exceed VDD by no more than 0.6V.
crrh2519.07
12/13/00
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
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