SYS32512LK-012.pdf 데이터시트 (총 11 페이지) - 파일 다운로드 SYS32512LK-012 데이타시트 다운로드

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SYS32512ZK/LK - 010/012/015
Issue 5.0 June 1999
Description
The SYS32512 is a 512K x 8 SRAM module in a ZIP
(ZK) or SIMM (LK & LKXA) packages with access
times of 12 and 15ns, with 10ns parts under
development. The device is available to
commercial and industrial temperature grade.
The LK SIMM package is designed for standard
SIMM sockets. The LKXA is designed to fit both
angled and standard sockets.
Block Diagram
A0~A18
/WE
/OE
/CS1
Features
• Access times of 10, 12 and 15ns.
• 5V + 10%.
• Commercial and Industrial temperature grades
• 72 pin ZIP and SIMM packages.
• Industry standard footprint.
• Power dissipation.
• Operating Power (32 Bit) 4.62W (max)
• Low power standby. (TTL) 1.32W (max)
(CMOS) 330mW (max)
• Completely Static Operation.
/CS2
/CS3
/CS4
Pin Definition
See page 2.
Pin Functions
512K x 8
SRAM
D0~7
512K x 8
SRAM
D8~15
512K x 8
SRAM
D16~23
512K x 8
SRAM
D24~D31
Package Details
Plastic 72 Pin ZIP (ZK)
Max. Dimensions (mm) - 97.80 x 20.61 x 5.90
Plastic 72 Pin SIMM (LK)
Max. Dimensions (mm) - 108.08 x 15.00 x 5.25
Plastic 72 Pin SIMM (LKXA)
Max. Dimensions (mm) - 108.08 x 20.32 x 4.55
Description
Address Input
Data Input/Output
Chip Select
Presence Detect
Write Enable
Output Enable
No Connect
Power
Ground
Signal
A0~A18
D0~D31
/CS1~4
PD0~3
/WE
/OE
NC
VCC
VSS

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Pin Definition - SYS32512 ZK/LK/LKXA
Pin Signal Pin Signal
1 NC 37 /CS4
2 NC 38 /CS3
3 PD2 39 A17
4 PD3 40 A16
5 VSS 41 /OE
6
PD0
42
VSS
7 PD1 43 D24
8 D0 44 D16
9 D8 45 D25
10 D1 46 D17
11 D9 47 D26
12 D2 48 D18
13 D10 49 D27
14 D3 50 D19
15 D11 51
A3
16 VCC 52 A10
17 A0 53 A4
18 A7 54 A11
19 A1 55 A5
20 A8 56 A12
21 A2 57 VCC
22 A9 58 A13
23 D12 59
A6
24 D4 60 D20
25 D13 61 D28
26 D5 62 D21
27 D14 63 D29
28 D6 64 D22
29 D15 65 D30
30 D7 66 D23
31 VSS 67 D31
32 /WE 68
VSS
33 A15 69 A18
34 A14 70
NC
35 /CS2 71
NC
36 /CS1 72
NC
Note
ZK : PD1=GND, PDO=PD2=PD3=OPEN
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Absolute Maximum Ratings(1)
Parameter
Voltage on any pin relative to VSS
Power Dissipation
Storage Temperature
Symbol
VT (2)
PT
TSTG
Min
-0.3
-55
Max
to +7.0
4.0
to +125
Unit
V
W
OC
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability
(2) VT can be -2.0V pulse of less than 2ns.
Recommended Operating Conditions
Parameter
Symbol Min
Supply Voltage
VCC 4.5
Input High Voltage
VIH
Input Low Voltage
VIL
Operating Temperature (Commercial) TA
2.2
-0.3
0
(Industrial)
TAI
-40
Typ Max Unit
5.0 5.5
V
- VCC+0.3 V
- 0.8 V
- 70 OC
- 85 OC (I Suffix)
DC Electrical Characteristics
(VCC=5V+10%, TA=0OC to 70OC)
Parameter
Symbol Test Condition
Min Typ Max Unit
Input Leakage Current
Address,
/OE, /WE
ILI
0V < VIN < VCC
-8 - 8 µA
Output Leakage
Current
Worst
Case
ILO /CS=VIH,VI/O=GND to VCC
-8 -
8
µA
Average Supply Current 32 Bit
ICC1
Min. Cycle, /CS=VIL, VIN =VIH
or VIL, IOUT=OmA
-
- 840 mA
Standby Supply Current TTL
ISB1 /CS=VIH
- - 240 mA
CMOS
ISB2
/CS>VCC-0.2V, 0.2V
>VIN>VCC-0.2V
- - 60 mA
Output Voltage Low
Output Voltage High
VOL
VOH
IOL=8.0mA
IOH=-4.0mA
--
2.4 -
0.4
-
V
V
Notes (1) /CS1~4 inputs operate simultaneously for 32 bit mode, in pairs for 16 bit mode and singly for
8 bit mode.
(2) Typical Values are at VCC=5.0V, TA=25OC and specified loading. /CS above refers to /CS1~4
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Capacitance
(VCC = 5.0V, TA = 25OC)
Param eter
Symbol Test Condition Min Typ Max Unit
Input Capacitance, (Address, /OE, /WE)
C IN1
V IN=0V
- - 32 pF
Input Capacitance, (Other)
C IN2
V IN=0V
- - 7 pF
O utput C apacitance, 8 bit m ode (worst case)
C I/O
V I/O=0V
- - 40 pF
Note : These Parameters are calculated not measured.
Test Conditions
Output Load
Input pulse levels : 0V to 3.0V
Input rise and fall times : 3ns
Input and Output timing reference levels : 1.5V
Output Load : See Load Diagram.
VCC = 5V+10%
I/O Pin
166Ω
1.76V
30pF
Operation Truth Table
/CS /OE /WE
HXX
L LH
LHL
LLL
L HH
Data Pins
High Impedence
Data Out
Data In
Data In
High Impedence
Supply Current
ISB1,ISB2
ICC1
ICC1
ICC1
ISB1,ISB2
Mode
Standby
Read
Write
Write
High Z
Notes : H=VIH : L=VIL : X=VIH or VIL
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Read Cycle
10 12 15
Parameter
Symbol Min Max Min Max Min Max Units
Read Cycle Time
tRC 10 - 12 - 15 - ns
Address Access Time
tAA - 10 - 12 - 15 ns
Chip Select Access Time
tACS - 10 - 12 - 15 ns
Output Enable to Output Valid
tOE - 5 - 6 - 7 ns
Output Hold From Address Change
tOH 3 - 3 - 3 - ns
Chip Selection to Output in Low Z
tCLZ 3 - 3 - 3 - ns
Output Enable to Output in Low Z
tOLZ
0
-
0
-
0
- ns
Chip Deselection to Output in High Z tCHZ 0 5 0 6 0 7 ns
Output Disable to Output in High Z
tOHZ 0 5 0 6 0 7 ns
Write Cycle
Parameter
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold time from Write Time
Output Active from End of Write
10 12 15
Symbol Min Max Min Max Min Max Units
tWC 10 - 12 - 15 - ns
tCW 7 - 8 - 10 - ns
tAW 7 - 8 - 10 - ns
tAS 0 - 0 - 0 - ns
tWP 7 - 8 - 10 - ns
tWR 0 - 0 - 0 - ns
tWHZ 0 5 0 6 0 10 ns
tDW 5 - 6 - 7 - ns
tDH 0 - 0 - 0 - ns
tOW 3 - 3 - 3 - ns
Under Development
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Issue 5.0 June 1999