AD9551.pdf 데이터시트 (총 30 페이지) - 파일 다운로드 AD9551 데이타시트 다운로드

No Preview Available !

www.DataSheet4U.com
Multiservice Clock Generator
AD9551
FEATURES
Translation between any two standard network rates
Dual reference inputs and dual clock outputs
Pin programmable for standard network rate translation
SPI programmable for arbitrary rational rate translation
Output frequencies from 10 MHz to 900 MHz
Input frequencies from 19.44 MHz to 806 MHz
On-chip VCO
Meets OC-192 high band jitter generation requirement
Supports standard forward error correction (FEC) rates
Supports holdover operation
Supports hitless switchover and phase build-out (even with
unequal reference frequencies)
SPI-compatible 3-wire programming interface
Single supply (3.3 V)
APPLICATIONS
Multiservice switches
Multiservice routers
Exact network clock frequency translation
General-purpose frequency translation
GENERAL DESCRIPTION
The AD9551 accepts one or two reference input signals to synthe-
size one or two output signals. The AD9551 uses a fractional-N
PLL that precisely translates the reference frequency to the desired
output frequency. The input receivers and output drivers provide
both single-ended and differential operation.
Reference conditioning and switchover circuitry internally
synchronizes the two references so that if one reference fails,
there is virtually no phase perturbation at the output.
The AD9551 uses an external crystal and an internal DCXO to
provide for holdover operation. If both references fail, the device
maintains a steady output signal.
The AD9551 provides pin-selectable, preset divider values for
standard (and FEC adjusted) network frequencies. The pin-
selectable frequencies include any combination of 15 possible
input frequencies and 16 possible output frequencies. A SPI
interface provides further flexibility by making it possible to
program almost any rational input/output frequency ratio.
The AD9551 is a clock generator that employs fractional-N-based
phase-locked loops (PLL) using sigma-delta (Σ-Δ) modulators
(SDMs). The fractional frequency synthesis capability enables
the device to meet the frequency and feature requirements for
multiservice switch applications. The AD9551 precisely generates
a wide range of standard frequencies when using any one of those
same standard frequencies as a timing base (reference). The
primary challenge of this function is the precise generation of the
desired output frequency because even a slight output frequency
error can cause problems for downstream clocking circuits in
the form of bit or cycle slips. The requirement for exact frequency
translation in such applications necessitates the use of a frac-
tional-N-based PLL architecture with variable modulus.
BASIC BLOCK DIAGRAM
CRYSTAL
(26MHz)
REFA
REFB
REFERENCE
CONDITIONING
AND SWITCH-
OVER
HOLDOVER
LOOP
PLL
OUTPUT
CIRCUITRY
OUT1
OUT2
PIN-DEFINED AND SERIAL
PROGRAMMING
Figure 1.
AD9551
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.

No Preview Available !

AD9551www.DataSheet4U.com
TABLE OF CONTENTS
Features .............................................................................................. 1 
Applications....................................................................................... 1 
General Description ......................................................................... 1 
Basic Block Diagram ........................................................................ 1 
Revision History ............................................................................... 2 
Functional Block Diagram .............................................................. 3 
Specifications..................................................................................... 4 
Reference Clock Input Characteristics ...................................... 4 
Output Characteristics................................................................. 4 
Jitter Characteristics (180 Hz Loop Bandwidth)...................... 5 
Crystal Oscillator Characteristics............................................... 5 
Power Consumption .................................................................... 5 
Logic Input Pins............................................................................ 6 
RESET Pin ..................................................................................... 6 
Logic Output Pins......................................................................... 6 
Serial Control Port ....................................................................... 6 
Serial Control Port Timing ......................................................... 7 
Absolute Maximum Ratings............................................................ 8 
ESD Caution.................................................................................. 8 
Pin Configuration and Function Descriptions............................. 9 
Typical Performance Characteristics ........................................... 11 
Preset Frequency Ratios................................................................. 14 
REVISION HISTORY
6/09—Rev. 0 to Rev. A
Changes to Figure 23...................................................................... 23
4/09—Revision 0: Initial Version
Theory of Operation ...................................................................... 16 
Operating Modes........................................................................ 16 
Component Blocks..................................................................... 16 
Holdover Mode........................................................................... 21 
Jitter Tolerance............................................................................ 21 
External Loop Filter Capacitor................................................. 21 
Output/Input Frequency Relationship .................................... 21 
Calculating Divider Values ....................................................... 22 
Low Dropout (LDO) Regulators .............................................. 24 
Applications Information .............................................................. 25 
Thermal Performance................................................................ 25 
Serial Control Port ......................................................................... 26 
Serial Control Port Pin Descriptions....................................... 26 
Operation of the Serial Control Port ....................................... 26 
Instruction Word (16 Bits)........................................................ 27 
MSB/LSB First Transfers ........................................................... 27 
Register Map ................................................................................... 29 
Register Map Descriptions........................................................ 32 
Outline Dimensions ....................................................................... 40 
Ordering Guide .......................................................................... 40 
Rev. A | Page 2 of 40

No Preview Available !

www.DataSheet4U.com
AD9551
The AD9551 is easily configured using the external control pins
(A[3:0], B[3:0], and Y[3:0]). The logic state of these pins sets pre-
defined divider values that establish a specific input-to-output
frequency ratio. For applications requiring other frequency ratios,
the user can override any of the preconfigured divider settings
via the serial port, which enables a very wide range of
applications.
The AD9551 includes reference signal processing blocks that
enable a smooth switching transition between two reference
inputs. This circuitry automatically detects the presence of the
reference input signals. If only one input is present, the device
uses it as the active reference. If both inputs are present, one
becomes the active reference and the other becomes the alter-
nate reference. The circuitry edge-aligns the backup reference
The AD9551 architecture consists of two cascaded PLL stages.
with the active reference. If the active reference fails, the circuitry
The first stage consists of fractional division (via SDM), followed
automatically switches to the backup reference (if available),
by a digital PLL that uses a crystal resonator-based DCXO. The
making it the new active reference. Meanwhile, if the failed
DCXO relies on an external crystal with a resonant frequency in
reference is once again available, it becomes the new backup
the range of 19.44 MHz to 52 MHz. The DCXO constitutes the
reference and is edge-aligned with the new active reference
first PLL, which operates within a narrow frequency range
(a precaution against failure of the new active reference).
(±50 ppm) around the crystal resonant frequency. This PLL has
a loop bandwidth of approximately 180 Hz, providing initial jitter
cleanup of the input reference signal. The second stage is a fre-
quency multiplying PLL that translates the first stage output
frequency (in the range of 19.44 MHz to 104 MHz) up to
~3.7 GHz. This PLL incorporates an SDM-based fractional
feedback divider that enables fractional frequency multiplication.
Programmable integer dividers at the output of this second PLL
establish a final output frequency of up to 900 MHz.
If neither reference can be used, the AD9551 supports a holdover
mode. Note that the external crystal is necessary to provide the
switchover and holdover functionality. It is also the clock source
for the reference synchronization and monitoring functions.
The AD9551 relies on a single external capacitor for the output
PLL loop filter. With proper termination, the output is compatible
with LVPECL, LVDS, or CMOS logic levels, although the AD9551
is implemented in a strictly CMOS process.
It is important to understand that the architecture of the AD9551
produces an output frequency that is most likely not coherent
The AD9551 operates over the extended industrial temperature
range of −40°C to +85°C.
with the input reference frequency. The reason is that the input
and crystal frequencies typically are not harmonically related
and neither are the output and crystal frequencies. As a result,
there is generally no relationship between the phase of the input
and output signals.
FUNCTIONAL BLOCK DIAGRAM
INPUT PLL
LOCKED
XTAL1 XTAL0
OUTPUT PLL
LOCKED
LF
REFA, REFA
2 fREFA
NA
SDMA
REFB, REFB
2 fREFB
NB
TEST
MUX
AD9551
19.44MHz MODE
P DIG.
F LOOP
D FILTER
DCXO
LOOP
CONFIGURATION
LOCK
DETECT
fIF
P
F
D
CHARGE
PUMP
3350MHz TO
4050MHz
VCO
4 TO
11
P0
1 TO
63
P1
fOUT1 2
SCLK, SDIO,
CS
SDMB
REFERENCE
MONITOR
SAMPLE RATE
CONTROL
3 REGISTER BANK
NA, MODA, FRACA
N = 4N1 + N0
N1 4/5
SDM
N
1 TO
63
P2
fOUT2 2
A[3:0]
B[3:0]
Y[3:0]
4
4 PRECONFIGURED
4 DIVIDER VALUES
NB, MODB, FRACB
N, MOD, FRAC, P0, P1, P2
19.44MHz MODE
P2, P1, P0
Figure 2.
Rev. A | Page 3 of 40
OUT1, OUT1
OUT2, OUT2

No Preview Available !

AD9551www.DataSheet4U.com
SPECIFICATIONS
Minimum and maximum values apply for full range of supply voltage and operating temperature variation. Typical values apply for VDD = 3.3 V,
TA = 25°C, unless otherwise noted.
REFERENCE CLOCK INPUT CHARACTERISTICS
Table 1.
Parameter
Min Typ Max Unit Test Conditions/Comments
FREQUENCY RANGE 191 806 MHz
INPUT CAPACITANCE
3 pF
INPUT RESISTANCE
6 kΩ Measured single-ended
DUTY CYCLE
40 60 %
REFERENCE CLOCK INPUT VOLTAGE SWING
Measured with a differential probe across
the input pins
Differential
250
mV Maximum magnitude across pin pair
Single-Ended
250
mV Peak-to-peak
1 The 19 MHz lower limit applies only to the 19.44 MHz operating mode.
OUTPUT CHARACTERISTICS
Table 2.
Parameter
LVPECL MODE
Differential Output Voltage Swing
Common-Mode Output Voltage
Frequency Range
Duty Cycle
Rise/Fall Time1 (20% to 80%)
LVDS MODE
Differential Output Voltage Swing
Balanced, VOD
Unbalanced, ΔVOD
Offset Voltage
Common Mode, VOS
Common-Mode Difference, ΔVOS
Short-Circuit Output Current
Frequency Range
Duty Cycle
Rise/Fall Time1 (20% to 80%)
CMOS MODE
Output Voltage High, VOH
IOH = 10 mA
IOH = 1 mA
Output Voltage Low, VOL
IOL = 10 mA
IOL = 1 mA
Frequency Range
Min Typ Max Unit
690
VDD − 1.77
0
40
765
VDD − 1.66
255
889
VDD − 1.20
900
60
305
mV
V
MHz
%
ps
Test Conditions/Comments
Output driver static
Output driver static
Up to 805 MHz output frequency
100 Ω termination between both pins of
the output driver
247
1.125
0
40
2.8
2.8
0
454
25
1.375
25
17 24
900
60
285 355
0.5
0.3
200
Rev. A | Page 4 of 40
mV Voltage swing between output pins;
output driver static
mV Absolute difference between voltage
swing of normal pin and inverted pin;
output driver static
V Output driver static
mV Voltage difference between output pins;
output driver static
mA
MHz
% Up to 805 MHz output frequency
ps 100 Ω termination between both pins of
the output driver
Output driver static; standard drive
strength setting
V
V
Output driver static; standard drive
strength setting
V
V
MHz 3.3 V CMOS; standard drive strength
setting

No Preview Available !

www.DataSheet4U.com
Parameter
Duty Cycle
Rise/Fall Time1 (20% to 80%)
Min Typ Max
45 55
500 745
1 The listed values are for the slower edge (rise or fall).
JITTER CHARACTERISTICS (180 HZ LOOP BANDWIDTH)
Table 3.
Parameter
JITTER GENERATION
12 kHz to 20 MHz
50 kHz to 80 MHz
4 MHz to 80 MHz
JITTER TRANSFER BANDWIDTH
Min Typ Max
1.3
0.8
0.5
0.6
0.1
180
JITTER TRANSFER PEAKING
0.1
CRYSTAL OSCILLATOR CHARACTERISTICS
Table 4.
Parameter
CRYSTAL FREQUENCY
Range
Tolerance
CRYSTAL MOTIONAL RESISTANCE
DCXO LOAD CAPACITANCE CONTROL
RANGE
Min
19
Typ
26
3 to 21
POWER CONSUMPTION
Table 5.
Parameter
TOTAL CURRENT
VDD CURRENT BY PIN
Pin 9
Pin 23
Pin 27
Pin 34
LVPECL OUTPUT DRIVER
Min Typ
169
24
78
36
36
38
Max
52
20
100
Max
195
27
84
42
42
AD9551
Unit Test Conditions/Comments
% At maximum output frequency
ps 3.3 V CMOS; standard drive strength
setting; 10 pF load
Unit Test Conditions/Comments
ps rms
ps rms
ps rms
ps rms
ps rms
Hz
dB
fIN = 19.44 MHz, fOUT = 622.08 MHz
fIN = 622.08 MHz, fOUT = 622.08 MHz
fIN = 19.44 MHz, fOUT = 622.08 MHz
fIN = 622.08 MHz, fOUT = 622.08 MHz
fIN = 622.08 MHz, fOUT = 622.08 MHz
See the Typical Performance Characteristics
section
See the Typical Performance Characteristics
section
Unit Test Conditions/Comments
MHz
ppm
Ω
pF Requires a crystal with a 10 pF load
specification
Unit Test Conditions/Comments
mA At maximum output frequency with both
output channels active
mA
mA
mA
mA
mA 900 MHz with 100 Ω termination between
both pins of the output driver
Rev. A | Page 5 of 40