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Fiber Channel/Ethernet Clock Generator IC,
7 Clock Outputs
AD9572
FEATURES
Fully integrated dual VCO/PLL cores
0.22 ps rms jitter from 0.637 MHz to 10 MHz at 106.25 MHz
0.19 ps rms jitter from 1.875 MHz to 20 MHz at 156.25 MHz
0.42 ps rms jitter from 12 kHz to 20 MHz at 125 MHz
Input crystal or clock frequency of 25 MHz
Preset divide ratios for 106.25 MHz, 156.25 MHz, 33.33 MHz,
100 MHz, and 125 MHz
Choice of LVPECL or LVDS output format
Integrated loop filters
Copy of reference clock output
Rates configured via strapping pins
0.71 W power dissipation (LVDS operation)
1.07 W power dissipation (LVPECL operation)
3.3 V operation
Space saving, 6 mm × 6 mm, 40-lead LFCSP
APPLICATIONS
Fiber channel line cards, switches, and routers
Gigabit Ethernet/PCIe support included
Low jitter, low phase noise clock generation
FUNCTIONAL BLOCK DIAGRAM
REFSEL
REFCLK
XTAL
OSC
LDO
VCO
CMOS
1 × 25MHz
LVPECL
OR LVDS
2 × 106.25MHz
AD9572
LDO
VCO
LVPECL
OR LVDS
LVPECL
OR LVDS
1 × 156.25MHz
2 × 100MHz
OR 125MHz
CMOS
1 × 33.33MHz
FORCE_LOW
FREQSEL
Figure 1.
GENERAL DESCRIPTION
The AD9572 provides a multioutput clock generator function
along with two on-chip PLL cores, optimized for fiber channel
line card applications that include an Ethernet interface. The
integer-N PLL design is based on the Analog Devices, Inc.,
proven portfolio of high performance, low jitter frequency
synthesizers to maximize network performance. Other applica-
tions with demanding phase noise and jitter requirements also
benefit from this part.
The PLL section consists of a low noise phase frequency
detector (PFD), a precision charge pump (CP), a low phase
noise voltage controlled oscillator (VCO), and a preprogrammed
feedback divider and output divider. By connecting an external
crystal or reference clock to the REFCLK pin, frequencies up to
156.25 MHz can be locked to the input reference. Each output
divider and feedback divider ratio is preprogrammed for the
required output rates.
A second PLL also operates as an integer-N synthesizer and
drives two LVPECL or LVDS output buffers for 106.25 MHz
operation. No external loop filter components are required, thus
conserving valuable design time and board space.
The AD9572 is available in a 40-lead, 6 mm × 6 mm lead frame
chip scale package (LFCSP) and can be operated from a single
3.3 V supply. The temperature range is −40°C to +85°C.
10G SFP+
CPU
ISLAND
16-PORT FIBRE CHANNEL ASIC
1 × 156.25MHz
2 × 106.25MHz
1 × 100MHz/125MHz
1 × 25MHz
1 × 33.33MHz
AD9572
QUAD SFP QUAD SFP QUAD SFP QUAD SFP
PHY
PHY
PHY
PHY
Figure 2. Typical Application
Rev. B
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2009-2011 Analog Devices, Inc. All rights reserved.

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AD9572* Product Page Quick Links
Last Content Update: 08/30/2016
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• AD9572 Evaluation Board
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Data Sheet
• AD9572: Fiber Channel/Ethernet Clock Generator IC, PLL
Core, Dividers, 7 Clock Outputs Data Sheet
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• AD9571/AD9572 IBIS Model
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• AD9572 Material Declaration
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AD9572
TABLE OF CONTENTS
Features .............................................................................................. 1 
Applications....................................................................................... 1 
Functional Block Diagram .............................................................. 1 
General Description ......................................................................... 1 
Revision History ............................................................................... 2 
Specifications..................................................................................... 3 
PLL Characteristics ...................................................................... 3 
LVDS Clock Output Jitter............................................................ 4 
LVPECL Clock Output Jitter....................................................... 5 
CMOS Clock Output Jitter.......................................................... 5 
Reference Input............................................................................. 5 
Clock Outputs ............................................................................... 6 
Timing Characteristics ................................................................ 6 
Control Pins .................................................................................. 7 
Power.............................................................................................. 7 
Crystal Oscillator.......................................................................... 7 
Timing Diagrams.............................................................................. 8 
Absolute Maximum Ratings............................................................ 9 
Thermal Resistance ...................................................................... 9 
REVISION HISTORY
/11—Rev. A to Rev. B
Changes to Output Rise Time, tRC2 Parameter and Output Fall
Time, tFC2 Parameter in Table 7....................................................... 6
11/10—Rev. 0 to Rev. A
Changes to Features.......................................................................... 1
Changes to Table 2............................................................................ 4
Changes to Table 3 and Table 4....................................................... 5
Changes to Table 7............................................................................ 6
Added Figure 7 and Figure 8......................................................... 11
Added Figure 14, Figure 15, and Figure 16 ................................. 13
Deleted Original Figure 16 and Figure 19................................... 16
ESD Caution...................................................................................9 
Pin Configuration and Function Descriptions........................... 10 
Typical Performance Characteristics ........................................... 13 
Terminology .................................................................................... 15 
Theory of Operation ...................................................................... 16 
Outputs ........................................................................................ 16 
Phase Frequency Detector (PFD) and Charge Pump............ 17 
Power Supply............................................................................... 17 
CMOS Clock Distribution ........................................................ 17 
LVPECL Clock Distribution ..................................................... 18 
LVDS Clock Distribution .......................................................... 18 
Reference Input........................................................................... 18 
Power and Grounding Considerations and Power Supply
Rejection...................................................................................... 19 
Outline Dimensions ....................................................................... 20 
Ordering Guide .......................................................................... 20 
Renumbered Figures Sequentially............................... Throughout
Changes to CMOS Clock Distribution Section.......................... 17
Changes to LVPECL Clock Distribution Section, Added
Figure 23 and Figure 24 ................................................................. 18
Changes to LVDS Clock Distribution Section, Added
Figure 26 .......................................................................................... 18
Changes to Reference Input Section ............................................ 18
Changes to Power and Grounding Considerations and Power
Supply Rejection Section ............................................................... 19
7/09—Revision 0: Initial Version
Rev. B | Page 2 of 20

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AD9572
SPECIFICATIONS
PLL CHARACTERISTICS
Typical (typ) is given for VS = 3.3 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
PHASE NOISE CHARACTERISTICS
PLL Noise (106.25 MHz LVDS Output)
At 1 kHz
At 10 kHz
At 100 kHz
At 1 MHz
At 10 MHz
At 30 MHz
PLL Noise (156.25 MHz LVDS Output)
At 1 kHz
At 10 kHz
At 100 kHz
At 1 MHz
At 10 MHz
At 30 MHz
PLL Noise (125 MHz LVDS Output)
At 1 kHz
At 10 kHz
At 100 kHz
At 1 MHz
At 10 MHz
At 30 MHz
PLL Noise (100 MHz LVDS Output)
At 1 kHz
At 10 kHz
At 100 kHz
At 1 MHz
At 10 MHz
At 30 MHz
PLL Noise (106.25 MHz LVPECL Output)
At 1 kHz
At 10 kHz
At 100 kHz
At 1 MHz
At 10 MHz
At 30 MHz
PLL Noise (156.25 MHz LVPECL Output)
At 1 kHz
At 10 kHz
At 100 kHz
At 1 MHz
At 10 MHz
At 30 MHz
Min
Typ
−123
−127
−129
−150
−152
−153
−118
−125
−126
−145
−151
−151
−119
−127
−128
−147
−151
−152
−121
−128
−130
−147
−150
−150
−121
−128
−129
−151
−154
−155
−119
−125
−126
−147
−152
−153
Max
Unit
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Test Conditions/Comments
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
Rev. B | Page 3 of 20

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AD9572
Parameter
PLL Noise (125 MHz LVPECL Output)
At 1 kHz
At 10 kHz
At 100 kHz
At 1 MHz
At 10 MHz
At 30 MHz
PLL Noise (100 MHz LVPECL Output)
At 1 kHz
At 10 kHz
At 100 kHz
At 1 MHz
At 10 MHz
At 30 MHz
PLL Noise (33.33 MHz CMOS Output)
At 1 kHz
At 10 kHz
At 100 kHz
At 1 MHz
At 5 MHz
Phase Noise (25 MHz CMOS Output)
At 1 kHz
At 10 kHz
At 100 kHz
At 1 MHz
At 5 MHz
Spurious Content1
PLL Figure of Merit
Min
Typ
Max Unit
Test Conditions/Comments
−122
−127
−128
−148
−152
−153
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
−122
−128
−130
−148
−150
−151
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
−130
−138
−139
−152
−152
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−133
−142
−148
−148
−148
−70
−217.5
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc
dBc/Hz
Dominant amplitude, all outputs active
1 When the 33.33 MHz, 100 MHz, and 125 MHz clocks are enabled simultaneously, a worst-case −50 dBc spurious content might be presented on Pin 21 and Pin 22 only.
LVDS CLOCK OUTPUT JITTER
Typical (typ) is given for VS = 3.3 V, TA = 25°C, unless otherwise noted.
Table 2.
Jitter Integration
Bandwidth (Typ)
12 kHz to 20 MHz
100 MHz
0.51
1.875 MHz to
20 MHz
637 kHz to 10 MHz
200 kHz to 10 MHz 0.32
12 kHz to 35 MHz
106.25 MHz
0.44
125 MHz 33M
= Off/On1
0.42/0.88
156.25 MHz
0.42
0.19
0.22
0.25/0.78
0.50 (off only)
Unit Test Conditions/Comments
ps LVDS output frequency combinations
rms are 1 × 156.25 MHz, 1 × 100 MHz, 1 ×
125 MHz, 2 × 106.25 MHz
ps LVDS output frequency combinations
rms are 1 × 156.25 MHz, 1 × 100 MHz, 1 ×
125 MHz, 2 × 106.25 MHz
ps LVDS output frequency combinations
rms are 1 × 156.25 MHz, 1 × 100 MHz, 1 ×
125 MHz, 2 × 106.25 MHz
ps LVDS output frequency combinations
rms are 1 × 156.25 MHz, 1 × 100 MHz, 1 ×
125 MHz, 2 × 106.25 MHz
ps LVDS output frequency combinations
rms are 1 × 156.25 MHz, 2 × 125 MHz, 2 ×
106.25 MHz
1 The typical 125 MHz rms jitter data is collected from the differential pair, Pin 21 and Pin 22, unless otherwise noted.
Rev. B | Page 4 of 20