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®
Data Sheet
September 27, 2006
ISL6261
FN9251.1
Single-Phase Core Regulator for IMVP-6®
Mobile CPUs
The ISL6261 is a single-phase buck regulator implementing
lntel® IMVP-6® protocol, with embedded gate drivers.
The heart of the ISL6261 is the patented R3 Technology™,
Intersil’s Robust Ripple Regulator modulator. Compared with
the traditional multi-phase buck regulator, the R3
Technology™ has faster transient response. This is due to
the R3 modulator commanding variable switching frequency
during a load transient.
lntel® Mobile Voltage Positioning (IMVP) is a smart voltage
regulation technology effectively reducing power dissipation
in lntel® Pentium processors. To boost battery life, the
ISL6261 supports DPRSLRVR (deeper sleep) function and
maximizes the efficiency via automatically changing
operation modes. At heavy load in the active mode, the
regulator commands the continuous conduction mode
(CCM) operation. When the CPU enters deeper sleep mode,
the ISL6261 enables diode emulation to maximize the
efficiency at light load. Asserting the FDE pin of the ISL6261
in deeper sleep mode will further decrease the switching
frequency at light load and increase the regulator efficiency.
A 7-bit digital-to-analog converter (DAC) allows dynamic
adjustment of the core output voltage from 0.300V to 1.500V.
The ISL6261 has 0.5% system voltage accuracy over
temperature.
A unity-gain differential amplifier provides remote voltage
sensing at the CPU die. This allows the voltage on the CPU
www.dDiaetatoShbeeeta4cUc.ucoramtely measured and regulated per lntel®
IMVP-6 specification. Current sensing can be implemented
through either lossless inductor DCR sensing or precise
resistor sensing. If DCR sensing is used, an NTC thermistor
network will thermally compensates the gain and the time
constant variations caused by the inductor DCR change.
Features
• Precision single-phase CORE voltage regulator
- 0.5% system accuracy over temperature
- Enhanced load line accuracy
• Internal gate driver with 2A driving capability
• Microprocessor voltage identification input
- 7-Bit VID input
- 0.300V to 1.500V in 12.5mV steps
- Support VID change on-the-fly
• Multiple current sensing schemes supported
- Lossless inductor DCR current sensing
- Precision resistive current sensing
• Thermal monitor
• User programmable switching frequency
• Differential remote voltage sensing at CPU die
• Overvoltage, undervoltage, and overcurrent protection
• Pb-free plus anneal available (RoHS compliant)
Ordering Information
PART NUMBER PART
(NOTE)
MARKING
TEMP
RANGE
(°C)
PACKAGE PKG.
(Pb-FREE) DWG. #
ISL6261CRZ
ISL6261CRZ -10 to +100 40 Ld 6x6 L40.6x6
QFN
ISL6261CRZ-T ISL6261CRZ -10 to +100 40 Ld 6x6 L40.6x6
QFN, T&R
ISL6261CR7Z ISL6261CR7Z -10 to +100 48 Ld 7x7 L48.7x7
QFN
ISL6261CR7Z-T ISL6261CR7Z -10 to +100 48 Ld 7x7 L48.7x7
QFN, T&R
ISL6261IRZ
ISL6261IRZ -40 to +100 40 Ld 6x6 L40.6x6
QFN
ISL6261IRZ-T ISL6261IRZ -40 to +100 40 Ld 6x6 L40.6x6
QFN, T&R
ISL6261IR7Z ISL6261IR7Z -40 to +100 48 Ld 7x7 L48.7x7
QFN
ISL6261IR7Z-T ISL6261IR7Z -40 to +100 48 Ld 7x7 L48.7x7
QFN, T&R
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved. R3 Technology™ is a trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.

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Pinouts
ISL6261
ISL6261
(40 LD QFN)
40 39 38 37 36 35 34 33 32 31
FDE 1
PGD_IN 2
RBIAS 3
VR_TT# 4
NTC 5
SOFT 6
OCSET 7
VW 8
COMP 9
FB 10
GND PAD
(BOTTOM)
30 VID2
29 VID1
28 VID0
27 VCCP
26 LGATE
25 VSSP
24 PHASE
23 UGATE
22 BOOT
21 NC
11 12 13 14 15 16 17 18 19 20
ISL6261
(48 LD QFN)
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48 47 46 45 44 43 42 41 40 39 38 37
PGOOD 1
FDE 2
PGD_IN 3
RBIAS 4
VR_TT# 5
NTC 6
SOFT 7
OCSET 8
VW 9
COMP 10
FB 11
NC 12
GND PAD
(BOTTOM)
36 NC
35 NC
34 NC
33 NC
32 NC
31 VCCP
30 LGATE
29 VSSP
28 PHASE
27 UGATE
26 BOOT
25 NC
13 14 15 16 17 18 19 20 21 22 23 24
2 FN9251.1
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ISL6261
Absolute Maximum Ratings
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +7V
Battery Voltage, VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+28V
Boot Voltage (BOOT) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V
Boot to Phase Voltage (BOOT-PHASE). . . . . . . . . -0.3V to +7V(DC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +9V(<10ns)
Phase Voltage (PHASE) . . . . . . . . . -7V (<20ns Pulse Width, 10µJ)
UGATE Voltage (UGATE) . . . . . . . . . . PHASE-0.3V (DC) to BOOT
. . . . . . . . . . . . . .PHASE-5V (<20ns Pulse Width, 10µJ) to BOOT
LGATE Voltage (LGATE) . . . . . . . . . . . . . . -0.3V (DC) to VDD+0.3V
. . . . . . . . . . . . . . . . -2.5V (<20ns Pulse Width, 5µJ) to VDD+0.3V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VDD +0.3V)
Open Drain Outputs, PGOOD, VR_TT# . . . . . . . . . . . . -0.3 to +7V
HBM ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>3kV
Thermal Information
Thermal Resistance (Typical)
θJA (°C/W)
θJC (°C/W)
6x6 QFN Package (Notes 1, 2) . . . . . . 33
5.5
7x7 QFN Package (Notes 1, 2) . . . . . . 30
5.5
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C
Recommended Operating Conditions
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5%
Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V to 21V
Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .-10°C to +125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications VDD = 5V, TA = -10°C to +100°C, Unless Otherwise Specified.
PARAMETER
SYMBOL
TEST CONDITIONS
INPUT POWER SUPPLY
+5V Supply Current
IVDD
VR_ON = 3.3V
VR_ON = 0V
+3.3V Supply Current
Battery Supply Current at VIN pin
POR (Power-On Reset) Threshold
SYSTEM AND REFERENCES
I3V3
IVIN
PORr
PORf
No load on CLK_EN# pin
VR_ON = 0, VIN = 25V
VDD Rising
VDD Falling
System Accuracy
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%Error
(Vcc_core)
No load, close loop, active mode,
TA = 0°C to +100°C,
VID = 0.75-1.5V
VID = 0.5-0.7375V
VID = 0.3-0.4875V
RBIAS Voltage
Boot Voltage
Maximum Output Voltage
RRBIAS
VBOOT
VCC_CORE
(max)
RRBIAS = 147kΩ
VID = [0000000]
Minimum Output Voltage
VCC_CORE
(min)
VID = [1100000]
VID Off State
VID = [1111111]
CHANNEL FREQUENCY
Nominal Channel Frequency
Adjustment Range
fSW RFSET = 7kΩ,
Vcomp = 2V
AMPLIFIERS
Droop Amplifier Offset
Error Amp DC Gain (Note 3)
AV0
MIN TYP MAX UNITS
- 3.1
--
--
--
- 4.35
3.85 4.1
3.6
1
1
1
4.5
-
mA
µA
µA
µA
V
V
-0.5 -
0.5
%
-8
-15
1.45
1.188
-
-
-
1.47
1.2
1.5
8
15
1.49
1.212
-
- 0.3
-
- 0.0
-
mV
mV
V
V
V
V
V
- 333
-
200 -
500
kHz
kHz
-0.3
- 90
0.3
-
mV
dB
3 FN9251.1
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ISL6261
Electrical Specifications VDD = 5V, TA = -10°C to +100°C, Unless Otherwise Specified. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
Error Amp Gain-Bandwidth Product
(Note 3)
GBW
CL = 20pF
-
Error Amp Slew Rate (Note 3)
FB Input Current
SOFT-START CURRENT
SR
IIN(FB)
CL = 20pF
-
-
Soft-start Current
ISS
Soft Geyserville Current
IGV
Soft Deeper Sleep Entry Current
IC4
Soft Deeper Sleep Exit Current
IC4EA
Soft Deeper Sleep Exit Current
IC4EB
GATE DRIVER DRIVING CAPABILITY (Note 4)
|SOFT - REF|>100mV
DPRSLPVR = 3.3V
DPRSLPVR = 3.3V
DPRSLPVR = 0V
-46
±175
-46
36
175
UGATE Source Resistance
RSRC(UGATE) 500mA Source Current
UGATE Source Current
ISRC(UGATE) VUGATE_PHASE = 2.5V
UGATE Sink Resistance
RSNK(UGATE) 500mA Sink Current
UGATE Sink Current
ISNK(UGATE) VUGATE_PHASE = 2.5V
LGATE Source Resistance
RSRC(LGATE) 500mA Source Current
LGATE Source Current
ISRC(LGATE) VLGATE = 2.5V
LGATE Sink Resistance
RSNK(LGATE) 500mA Sink Current
LGATE Sink Current
ISNK(LGATE) VLGATE = 2.5V
UGATE to PHASE Resistance
RP(UGATE)
GATE DRIVER SWITCHING TIMING (Refer to Timing Diagram)
-
-
-
-
-
-
-
-
-
UGATE Turn-on Propagation Delay
LGATE Turn-on Propagation Delay
BOOTSTRAP DIODE
tPDHU
tPDHL
PVCC = 5V, Output Unloaded
PVCC = 5V, Output Unloaded
20
7
Forward Voltage
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Leakage
POWER GOOD and PROTECTION MONITOR
VDDP = 5V, Forward Bias Current = 2mA
VR = 16V
0.43
-
PGOOD Low Voltage
PGOOD Leakage Current
PGOOD Delay
VOL
IOH
tpgd
IPGOOD = 4mA
PGOOD = 3.3V
CLK_EN# Low to PGOOD High
-
-1
5.5
Overvoltage Threshold
Severe Overvoltage Threshold
OCSET Reference Current
OVH
OVHS
VO rising above setpoint >1ms
VO rising above setpoint >0.5µs
I(Rbias) = 10µA
160
1.675
9.8
OC Threshold Offset
DROOP rising above OCSET >120µs
-3.5
Undervoltage Threshold
(VDIFF-SOFT)
UVf VO below set point for >1ms
-360
LOGIC THRESHOLDS
VR_ON, DPRSLPVR and PGD_IN
Input Low
VIL(3.3V)
-
VR_ON, DPRSLPVR and PGD_IN
Input High
VIH(3.3V)
2.3
TYP
18
5.0
10
-41
±200
-41
41
200
1
2
1
2
1
2
0.5
4
1.1
30
15
0.58
-
0.11
-
6.8
200
1.7
10
-300
-
-
MAX
-
-
150
-36
±225
-36
46
225
1.5
-
1.5
-
1.5
-
0.9
-
-
44
30
0.67
1
0.4
1
8.1
240
1.725
10.2
3.5
-240
1
-
UNITS
MHz
V/µs
nA
µA
µA
µA
µA
µA
Ω
A
Ω
A
Ω
A
Ω
A
kΩ
ns
ns
V
μA
V
µA
ms
mV
V
µA
mV
mV
V
V
4 FN9251.1
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ISL6261
Electrical Specifications VDD = 5V, TA = -10°C to +100°C, Unless Otherwise Specified. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
Leakage Current on VR_ON and
PGD_IN
Leakage Current on DPRSLPVR
DAC(VID0-VID6), PSI# and
DPRSTP# Input Low
IIL
IIH
IIL_DPRSLP
IIH_DPRSLP
VIL(1.0V)
Logic input is low
Logic input is high
DPRSLPVR logic input is low
DPRSLPVR logic input is high
-1
-
-1
-
-
DAC(VID0-VID6), PSI# and
DPRSTP# Input High
VIH(1.0V)
0.7
Leakage Current of DAC(VID0-
VID6) and DPRSTP#
THERMAL MONITOR
IIL DPRSLPVR logic input is low
IIH DPRSLPVR logic input is high
-1
-
NTC Source Current
NTC = 1.3V
53
Over-temperature Threshold
V(NTC) falling
1.17
VR_TT# Low Output Resistance
CLK_EN# OUTPUT LEVELS
RTT I = 20mA
-
CLK_EN# High Output Voltage
VOH 3V3 = 3.3V, I = -4mA
CLK_EN# Low Output Voltage
VOL
ICLK_EN# = 4mA
NOTES:
3. Guaranteed by characterization.
4. Guaranteed by design.
2.9
-
TYP
0
0
0
0.45
-
-
0
0.45
60
1.2
5
3.1
0.18
MAX
-
1
-
1
0.3
-
-
1
67
1.25
9
-
0.4
UNITS
μA
μA
μA
μA
V
V
μA
μA
µA
V
V
V
Gate Driver Timing Diagram
PWM
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UGATE
tPDHU
tRU
tFU
1V
LGATE
tFL
1V
tPDHL
tRL
5 FN9251.1
September 27, 2006