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MCP621/1S/2/3/4/5/9
20 MHz, 200 µV Op Amps with mCal
Features:
• Gain-Bandwidth Product: 20 MHz (typical)
• Slew Rate: 30 V/µs
• Low Input Offset: ±200 µV (maximum)
• Low Input Bias Current: 5 pA (typical)
• Noise: 13 nV/Hz, at 1 MHz
• Ease-of-Use:
- Unity-Gain Stable
- Rail-to-Rail Output
- Input Range incl. Negative Rail
- No Phase Reversal
• Supply Voltage Range: +2.5V to +5.5V
• High Output Current: ±70 mA
• Supply Current: 2.5 mA/Ch (typical)
• Low-Power Mode: 5 µA/Ch
• Small Packages: SOT23-5, DFN
• Extended Temperature Range: -40°C to +125°C
Typical Applications:
• Optical Detector Amplifier
• Barcode Scanners
• Multi-Pole Active Filter
• Driving A/D Converters
• Fast Low-Side Current Sensing
• Power Amplifier Control Loops
• Consumer Audio
Design Aids:
• SPICE Macro Models
• FilterLab® Software
• Microchip Advanced Part Selector (MAPS)
• Analog Demonstration and Evaluation Boards
• Application Notes
Description:
The Microchip Technology Inc. MCP621/1S/2/3/4/5/9
family of high bandwidth and high slew rate operational
amplifiers features low offset. At power-up, these op
amps are self-calibrated using mCal. Some package
options also provide a Calibration/Chip Select pin
(CAL/CS) that supports a Low-Power mode of
operation, with offset calibration at the time normal
operation is re-started. These amplifiers are optimized
for high speed, low noise and distortion, single-supply
operation with rail-to-rail output and an input that
includes the negative rail.
This family is offered in single (MCP621 and
MCP621S), single with CAL/CS pin (MCP623), dual
(MCP622), dual with CAL/CS pins (MCP625), quad
(MCP624) and quad with CAL/CS pins (MCP629). All
devices are fully specified from -40°C to +125°C.
Typical Application Circuit
Detector Amplifier with 350kHz
2nd-order MFB Low pass Filter
CF 3 pF
Photo Detector
RF
100 k
ID
100 nA
CD
30 pF
A
VREF
2.61 k26.1 k
270 pF
MCP622
294
100 pF
B
VREF
VOUT
High Gain-Bandwidth Op Amp Portfolio
Model Family
Channels/Package
MCP621/1S/2/3/4/5/9
MCP631/2/3/4/5/9
MCP651/1S/2/3/4/5/9
MCP660/1/2/3/4/5/9
1, 2, 4
1, 2, 4
1, 2, 4
1, 2, 3, 4
Gain Bandwidth
20 MHz
24 MHz
50 MHz
60 MHz
VOS (max.)
0.2 mV
8.0 mV
0.2 mV
8.0 mV
IQ/Ch (typ.)
2.5 mA
2.5 mA
6.0 mA
6.0 mA
2009-2014 Microchip Technology Inc.
DS20002188D-page 1

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MCP621/1S/2/3/4/5/9
Package Types
MCP621
SOIC
NC 1
VIN– 2
VIN+ 3
VSS 4
8 CAL/CS
7 VDD
6 VOUT
5 VCAL
MCP621
2x3 TDFN *
MCP621S
SOT-23-5
MCP624
SOIC, TSSOP
NC 1
8 CAL/CS VOUT 1
VIN– 2 EP 7 VDD
VIN+ 3 9 6 VOUT
VSS 2
VSS 4
5 VCAL
VIN+ 3
5 VDD
4 VIN-
VOUTA 1
VINA- 2
VINA+ 3
VDD 4
VINB+ 5
VINB- 6
VOUTB 7
14 VOUTD
13 VIND-
12 VIND+
11 VSS
10 VINC+
9 VINC-
8 VOUTC
MCP622
3x3 DFN *
MCP622
SOIC
MCP623
SOT-23-6
MCP629
4x4 QFN*
VOUTA 1
8 VDD
VOUTA 1
VINA– 2 EP 7 VOUTB
VINA+ 3 9 6 VINB
VSS 4
5 VINB+
VINA– 2
VINA+ 3
VSS 4
MCP625
3x3 DFN *
VOUTA 1
VINA– 2
VINA+ 3
VSS 4
CALA/CSA 5
10 VDD
EP
11
9 VOUTB
8 VINB
7 VINB+
6 CALB/CSB
8 VDD
7 VOUTB
6 VINB
5 VINB+
VOUT 1
VSS 2
VIN+ 3
6 VDD
5 CAL/CS
4 VIN-
16 15 14 13
VINA- 1
12 VIND+
MCP625
MSOP
VOUTA 1
VINA2
VINA+ 3
VSS 4
10 VDD
9 VOUTB
8 VINB
7 VINB+
VINA+ 2
VDD 3
VINB+ 4
5
EP
17
67
11 VSS
10 VINC+
9 VINC-
8
CALA/CSA 5
6 CALB/CSB
* Includes Exposed Thermal Pad (EP); see Table 3-1.
DS20002188D-page 2
2009-2014 Microchip Technology Inc.

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MCP621/1S/2/3/4/5/9
1.0 ELECTRICAL CHARACTERISTICS
1.1 Absolute Maximum Ratings †
VDD – VSS .......................................................................6.5V
Current at Input Pins ....................................................±2 mA
Analog Inputs (VIN+ and VIN–) †† . VSS – 1.0V to VDD + 1.0V
All Other Inputs and Outputs ......... VSS – 0.3V to VDD + 0.3V
Output Short Circuit Current ................................ Continuous
Current at Output and Supply Pins ..........................±150 mA
Storage Temperature ...................................-65°C to +150°C
Max. Junction Temperature ........................................ +150°C
ESD protection on all pins (HBM, MM)  1 kV, 200V
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at those or any other
conditions above those indicated in the operational
listings of this specification is not implied. Exposure to
maximum rating conditions for extended periods may
affect device reliability.
†† See Section 4.2.2, Input Voltage and Current
Limits.
1.2 Specifications
TABLE 1-1: DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND,
VCM = VDD/3, VOUT VDD/2, VL = VDD/2, RL = 2 kto VL and CAL/CS = VSS (refer to Figure 1-2).
Parameters
Sym.
Min.
Typ.
Max. Units
Conditions
Input Offset
Input Offset Voltage
VOS -200
+200
µV After calibration (Note 1)
Input Offset Voltage Trim Step
Size
VOSTRM
37 200 µV (Note 2)
Input Offset Voltage Drift
VOS/TA
±2.0
— µV/°C TA = -40°C to +125°C
Power Supply Rejection Ratio PSRR
61
76
— dB
Input Current and Impedance
Input Bias Current
Across Temperature
Across Temperature
Input Offset Current
Common Mode Input
Impedance
Differential Input Impedance
Common Mode
IB
IB
IB
IOS
ZCM
ZDIFF
— 5 — pA
— 100 — pA TA = +85°C
1700
5,000
pA TA = +125°C
— ±10 — pA
— 1013||9 — ||pF
— 1013||2 — ||pF
Common Mode Input Voltage
Range
VCMR VSS 0.3 — VDD 1.3 V (Note 3)
Common Mode Rejection Ratio CMRR
65
81
— dB VDD = 2.5V, VCM = -0.3 to
1.2V
CMRR
68
84
— dB VDD = 5.5V, VCM = -0.3 to
4.2V
Open-Loop Gain
DC Open-Loop Gain
(large signal)
AOL 88 117 — dB VDD = 2.5V,
VOUT = 0.3V to 2.2V
AOL 94 126 — dB VDD = 5.5V,
VOUT = 0.3V to 5.2V
Note 1: Describes the offset (under the specified conditions) right after power-up, or just after the CAL/CS pin is
toggled. Thus, 1/f noise effects (an apparent wander in VOS; see Figure 2-35) are not included.
2: Increment between adjacent VOS trim points; Figure 2-3 shows how this affects the VOS repeatability.
3: See Figure 2-6 and Figure 2-7 for temperature effects.
4: The ISC specifications are for design guidance only; they are not tested.
2009-2014 Microchip Technology Inc.
DS20002188D-page 3

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MCP621/1S/2/3/4/5/9
TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND,
VCM = VDD/3, VOUT VDD/2, VL = VDD/2, RL = 2 kto VL and CAL/CS = VSS (refer to Figure 1-2).
Parameters
Sym.
Min.
Typ.
Max. Units
Conditions
Output
Maximum Output Voltage Swing VOL, VOH VSS + 20 — VDD 20 mV VDD = 2.5V, G = +2,
0.5V Input Overdrive
VOL, VOH VSS + 40 — VDD 40 mV VDD = 5.5V, G = +2,
0.5V Input Overdrive
Output Short Circuit Current
Calibration Input
ISC
±40
±85
±130
mA VDD = 2.5V (Note 4)
ISC
±35
±70
±110
mA VDD = 5.5V (Note 4)
Calibration Input Voltage Range
Internal Calibration Voltage
Input Impedance
Power Supply
VCALRNG
VCAL
ZCAL
VSS + 0.1 — VDD – 1.4 mV VCAL pin externally driven
0.323VDD 0.333VDD 0.343VDD
VCAL pin open
— 100 || 5 — k||pF
Supply Voltage
Quiescent Current per Amplifier
POR Input Threshold, Low
VDD
IQ
VPRL
2.5
1.2
1.15
2.5
1.40
5.5 V
3.6 mA IO = 0
—V
POR Input Threshold, High
VPRH — 1.40 1.65 V
Note 1:
2:
3:
4:
Describes the offset (under the specified conditions) right after power-up, or just after the CAL/CS pin is
toggled. Thus, 1/f noise effects (an apparent wander in VOS; see Figure 2-35) are not included.
Increment between adjacent VOS trim points; Figure 2-3 shows how this affects the VOS repeatability.
See Figure 2-6 and Figure 2-7 for temperature effects.
The ISC specifications are for design guidance only; they are not tested.
TABLE 1-2: AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND,
VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 2 kto VL, CL = 50 pF and CAL/CS = VSS (refer to Figure 1-2).
Parameters
Sym. Min. Typ. Max. Units
Conditions
AC Response
Gain Bandwidth Product
Phase Margin
Open-Loop Output Impedance
AC Distortion
Total Harmonic Distortion plus
Noise
Step Response
Rise Time, 10% to 90%
Slew Rate
Noise
Input Noise Voltage
Input Noise Voltage Density
Input Noise Current Density
GBWP — 20 —
PM — 60 —
ROUT
15
THD+N — 0.0018 —
tr — 13 —
SR — 10 —
MHz
°
G = +1
% G = +1, VOUT = 2VP-P, f = 1 kHz,
VDD = 5.5V, BW = 80 kHz
ns G = +1, VOUT = 100 mVP-P
V/µs G = +1
Eni — 20 — µVP-P f = 0.1 Hz to 10 Hz
eni — 13 — nV/Hz f = 1 MHz
ini 4 — fA/Hz f = 1 kHz
DS20002188D-page 4
2009-2014 Microchip Technology Inc.

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MCP621/1S/2/3/4/5/9
TABLE 1-3: DIGITAL ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2,
VOUT VDD/2, VL = VDD/2, RL = 2 kto VL, CL = 50 pF and CAL/CS = VSS (refer to Figure 1-1 and Figure 1-2).
Parameters
Sym. Min. Typ. Max. Units
Conditions
CAL/CS Low Specifications
CAL/CS Logic Threshold, Low
CAL/CS Input Current, Low
CAL/CS High Specifications
VIL VSS — 0.2VDD V
ICSL — 0 — nA CAL/CS = 0V
CAL/CS Logic Threshold, High
CAL/CS Input Current, High
GND Current
CAL/CS Internal Pull-Down
Resistor
VIH
ICSH
ISS
ISS
ISS
ISS
RPD
0.8VDD
— 0.7
-3.5 -1.8
-8 -4
-5 -2.5
-10 -5
—5
VDD
V
µA CAL/CS = VDD
µA Single, CAL/CS = VDD = 2.5V
µA Single, CAL/CS = VDD = 5.5V
µA Dual, CAL/CS = VDD = 2.5V
µA Dual, CAL/CS = VDD = 5.5V
M
Amplifier Output Leakage
POR Dynamic Specifications
VDD Low to Amplifier Off Time
(output goes High Z)
VDD High to Amplifier On Time
(including calibration)
IO(LEAK)
50
tPOFF
— 200 —
tPON
100 200 300
nA CAL/CS = VDD, TA = 125°C
ns G = +1 V/V, VL = VSS,
VDD = 2.5V to 0V step to VOUT = 0.1
(2.5V)
ms G = +1 V/V, VL = VSS,
VDD = 0V to 2.5V step to VOUT = 0.9
(2.5V)
CAL/CS Dynamic Specifications
CAL/CS Input Hysteresis
VHYST
0.25
V
CAL/CS Setup Time
(between CAL/CS edges)
tCSU
1 — — µs G = +1 V/V, VL = VSS (Notes 2, 3, 4)
CAL/CS = 0.8VDD to VOUT = 0.1
(VDD/2)
CAL/CS High to Amplifier Off Time tCOFF
(output goes High Z)
— 200 —
ns G = +1 V/V, VL = VSS,
CAL/CS = 0.8VDD to VOUT = 0.1
(VDD/2)
CAL/CS Low to Amplifier On Time
(including calibration)
tCON
3
4 ms G = +1 V/V, VL = VSS, MCP621 and
MCP625, CAL/CS = 0.2VDD to
VOUT = 0.9 (VDD/2)
tCON — 6
8 ms G = +1 V/V, VL = VSS, MCP629,
CAL/CS = 0.2VDD to
VOUT = 0.9 (VDD/2)
Note 1: The MCP622 single, MCP625 dual and MCP629 quad have their CAL/CS inputs internally pulled down to VSS (0V).
2: This time ensures that the internal logic recognizes the edge. However, for the rising edge case, if CAL/CS is raised
before the calibration is complete, the calibration will be aborted and the part will return to Low-Power mode.
3: For the MCP625 dual, there is an additional constraint. CALA/CSA and CALB/CSB can be toggled simultaneously
(within a time much smaller than tCSU) to make both op amps perform the same function simultaneously. If they are
toggled independently, then CALA/CSA (CALB/CSB) cannot be allowed to toggle while op amp B (op amp A) is in
Calibration mode; allow more than the maximum tCON time (4 ms) before the other side is toggled.
4: For the MCP629 quad, there is an additional constraint. CALAD/CSAD and CALBC/CSBC can be toggled simultaneously
(within a time much smaller than tCSU) to make all four op amps perform the same function simultaneously, and the
maximum tCON time is approximately doubled (8 ms). If they are toggled independently, then CALAD/CSAD
(CALBC/CSBC) cannot be allowed to toggle while op amps B and C (op amps A and D) are in Calibration mode; allow
more than the maximum tCON time (8 ms) before the other side is toggled.
2009-2014 Microchip Technology Inc.
DS20002188D-page 5