K4M51323LC-L.pdf 데이터시트 (총 12 페이지) - 파일 다운로드 K4M51323LC-L 데이타시트 다운로드

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K4M51323LC - S(D)N/G/L/F
Mobile-SDRAM
4M x 32Bit x 4 Banks Mobile SDRAM in 90FBGA
FEATURES
• VDD/VDDQ = 2.5V/2.5V
• LVCMOS compatible with multiplexed address.
• Four banks operation.
• MRS cycle with address key programs.
-. CAS latency (1, 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
• EMRS cycle with address key programs.
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation.
• Special Function Support.
-. PASR (Partial Array Self Refresh).
-. Internal TCSR (Temperature Compensated Self Refresh)
• DQM for masking.
• Auto refresh.
• 64ms refresh period (8K cycle).
• Commercial Temperature Operation (-25°C ~ 70°C).
• Extended Temperature Operation (-25°C ~ 85°C).
• 90Balls FBGA ( -SXXX -Pb, -DXXX -Pb Free).
GENERAL DESCRIPTION
The K4M51323LC is 536,870,912 bits synchronous high data
rate Dynamic RAM organized as 4 x 4,196,304 words by 32 bits,
fabricated with SAMSUNG’s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock and I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst lengths and programmable latencies allow the same
device to be useful for a variety of high bandwidth and high per-
formance memory system applications.
ORDERING INFORMATION
Part No.
Max Freq.
K4M51323LC-S(D)N/G/L/F75
133MHz(CL=3), 111MHz(CL=2)
K4M51323LC-S(D)N/G/L/F7L*1
133MHz(CL=3), 83MHz(CL=2)
- S(D)N/G : Low Power, Extended Temperature(-25°C ~ 85°C)
- S(D)L/F : Low Power, Commercial Temperature(-25°C ~ 70°C)
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NOTES :
1. In case of 40MHz Frequency, CL1 can be supported.
Interface
LVCMOS
Package
90 FBGA Pb
(Pb Free)
Address configuration
Organization
16Mx32
Bank
BA0,BA1
Row
A0 - A12
Column Address
A0 - A8
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PRO-
VIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could
result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or pro-
visions may apply.
1 March 2006

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K4M51323LC - S(D)N/G/L/F
FUNCTIONAL BLOCK DIAGRAM
Mobile-SDRAM
Bank Select
Data Input Register
CLK
ADD
4M x 32
4M x 32
4M x 32
4M x 32
Column Decoder
LCKE
LRAS
LCBR
LWE
LCAS
Latency & Burst Length
Programming Register
LWCBR
Timing Register
CLK CKE CS RAS CAS WE DQM
LWE
LDQM
DQi
LDQM
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2 March 2006

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K4M51323LC - S(D)N/G/L/F
Mobile-SDRAM
9
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
Package Dimension and Pin Configuration
< Bottom View*1 >
E1
8765432
1
< Top View*2 >
90Ball(6x15) FBGA
1237
A DQ26 DQ24 VSS VDD
B DQ28 VDDQ VSSQ VDDQ
C VSSQ DQ27 DQ25 DQ22
D VSSQ DQ29 DQ30 DQ17
E VDDQ DQ31 NC
NC
F VSS DQM3 A3
A2
G A4 A5 A6 A10
H A7
A8 A12 NC
J CLK CKE A9 BA0
K DQM1 NC
NC CAS
L VDDQ DQ8 VSS VDD
M VSSQ DQ10 DQ9 DQ6
N VSSQ DQ12 DQ14 DQ1
P DQ11 VDDQ VSSQ VDDQ
R DQ13 DQ15 VSS VDD
E
8
DQ23
VSSQ
DQ20
DQ18
DQ16
DQM2
A0
BA1
CS
WE
DQ7
DQ5
DQ3
VSSQ
DQ0
9
DQ21
DQ19
VDDQ
VDDQ
VSSQ
VDD
A1
A11
RAS
DQM0
VSSQ
VDDQ
VDDQ
DQ4
DQ2
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z
b
< Top View*2 >
#A1 Ball Origin Indicator
A
A1
Pin Name
CLK
CS
CKE
A0 ~ A12
BA0 ~ BA1
RAS
CAS
WE
DQM0 ~ DQM3
DQ0 ~ 31
VDD/VSS
VDDQ/VSSQ
Pin Function
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
[Unit::mm]
Symbol
A
A1
E
E1
D
D1
e
b
z
Min
-
0.25
10.9
-
12.9
-
-
0.45
-
Typ
-
-
11.0
6.40
13.0
11.2
0.80
0.50
-
Max
1.00
-
11.1
-
13.1
-
-
0.55
0.10
3 March 2006

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K4M51323LC - S(D)N/G/L/F
Mobile-SDRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Voltage on any pin relative to Vss
VIN, VOUT
-1.0 ~ 3.6
Voltage on VDD supply relative to Vss
VDD, VDDQ
-1.0 ~ 3.6
Storage temperature
TSTG
-55 ~ +150
Power dissipation
PD 1.0
Short circuit current
IOS
NOTES:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
50
Unit
V
V
°C
W
mA
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 85°C for Extended, -25 to 70°C for Commercial)
Parameter
Symbol
Min
Typ
Max Unit
Note
Supply voltage
VDD 2.3 2.5 2.7
VDDQ
2.3
2.5
2.7
V
V
1
1
Input logic high voltage
VIH 0.8 x VDDQ
-
VDDQ + 0.3
V
2
Input logic low voltage
VIL -0.3 0 0.3 V
3
Output logic high voltage
VOH
VDDQ -0.2
-
- V IOH = -0.1mA
Output logic low voltage
VOL -
- 0.2 V IOL = 0.1mA
Input leakage current
ILI -10 - 10 uA
4
NOTES :
1. Under all conditions, VDDQ must be less than or equal to VDD.
2. VIH (max) = 3.0V AC.The overshoot voltage duration is 3ns.
3. VIL (min) = -1.0V AC. The undershoot voltage duration is 3ns.
4. Any input 0V VIN VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs.
5. Dout is disabled, 0V VOUT VDDQ.
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CAPACITANCE (VDD = 2.5V, TA = 23°C, f = 1MHz, VREF =0.9V ± 50 mV)
Pin
Symbol
Min
Clock
CCLK
1.5
RAS, CAS, WE, CS, CKE
CIN 1.5
DQM
CIN 1.5
Address
CADD
1.5
DQ0 ~ DQ31
COUT
2.0
Max
3.5
3.0
3.0
3.0
4.5
Unit
pF
pF
pF
pF
pF
Note
4 March 2006

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K4M51323LC - S(D)N/G/L/F
Mobile-SDRAM
DC CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 85°C for Extended, -25 to 70°C for Commercial)
Parameter
Symbol
Test Condition
Version
-75 -7L
Unit Note
Operating Current
(One Bank Active)
Burst length = 1
ICC1 tRC tRC(min)
IO = 0 mA
110 110 mA 1
Precharge Standby Current
in power-down mode
Precharge Standby Current
in non power-down mode
ICC2P CKE VIL(max), tCC = 10ns
ICC2PS CKE & CLK VIL(max), tCC =
ICC2N
CKE VIH(min), CS VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
ICC2NS
CKE VIH(min), CLK VIL(max), tCC =
Input signals are stable
1.0
1.0
15
5
mA
mA
Active Standby Current
in power-down mode
Active Standby Current
in non power-down mode
(One Bank Active)
ICC3P CKE VIL(max), tCC = 10ns
ICC3PS CKE & CLK VIL(max), tCC =
ICC3N
CKE VIH(min), CS VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
ICC3NS
CKE VIH(min), CLK VIL(max), tCC =
Input signals are stable
8
8
30
20
mA
mA
mA
Operating Current
(Burst Mode)
ICC4
IO = 0 mA
Page burst
4Banks Activated
tCCD = 2CLKs
150 105 mA 1
Refresh Current
Self Refresh Current
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ICC5 tRC tRC(min)
ICC6 CKE 0.2V
-G/F
-N/L
Internal TCSR
Full Array
1/2 of Full Array
1/4 of Full Array
180 180 mA 2
800 uA
45 *4
500
85/70 °C 3
800
450 700 uA
425 625
NOTES:
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Internal TCSR can be supported.
In commercial Temp : 45°C/70°C, In extended Temp : 45°C/85°C
4. It has +/-5 °C tolerance.
5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ).
5 March 2006