ISL62881.pdf 데이터시트 (총 30 페이지) - 파일 다운로드 ISL62881 데이타시트 다운로드

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Single-Phase PWM Regulator for IMVP-6.5Mobile
CPUs and GPUs
ISL62881, ISL62881B
The ISL62881 is a single-phase PWM buck regulator for
miroprocessor or graphics processor core power supply.
It uses an integrated gate drivers to provide a complete
solution. The PWM modulator of ISL62881 is based on
Intersil's Robust Ripple Regulator (R3) technology™.
Compared with traditional modulators, the R3™
modulator commands variable switching frequency
during load transients, achieving faster transient
response. With the same modulator, the switching
frequency is reduced at light load, increasing the
regulator efficiency.
The ISL62881 can be configured as CPU or graphics
Vcore controller and is fully compliant with IMVP-6.5
specifications. It responds to DPRSLPVR signals by
entering/exiting diode emulation mode. It reports the
regulator output current through the IMON pin. It senses
the current by using either discrete resistor or inductor
DCR whose variation over-temperature can be thermally
compensated by a single NTC thermistor. It uses
differential remote voltage sensing to accurately regulate
the processor die voltage. The adaptive body diode
conduction time reduction function minimizes the body
diode conduction loss in diode emulation mode.
User-selectable overshoot reduction function offers an
option to aggressively reduce the output capacitors as
well as the option to disable it for users concerned about
increased system thermal stress.
Maintaining all the ISL62881 functions, the ISL62881B
offers VR_TT# function for thermal throttling control. It
www.aDlastoaSohfefeetr4sUt.hcoemsplit LGATE function to further improve
light load efficiency.
Features
• Precision Core Voltage Regulation
- 0.5% System Accuracy Over-Temperature
- Enhanced Load Line Accuracy
• Voltage Identification Input
- 7-Bit VID Input, 0V to 1.500V in 12.5mV Steps
- Supports VID Changes On-The-Fly
• Supports Multiple Current Sensing Methods
- Lossless Inductor DCR Current Sensing
- Precision Resistor Current Sensing
• Superior Noise Immunity and Transient Response
• Current Monitor
• Differential Remote Voltage Sensing
• High Efficiency Across Entire Load Range
• Integrated Gate Driver
• Split LGATE Driver to Increase Light-Load Efficiency
(For ISL62881B)
• Adaptive Body Diode Conduction Time Reduction
• User-selectable Overshoot Reduction Function
• Capable of Disabling the Droop Function
• Audio-filtering for GPU Application
• Small Footprint 28 Ld 4x4 TQFN Package
• Pb-Free (RoHS Compliant)
Applications
• Notebook Computers
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL62881HRTZ*
628 81HRTZ
-10 to +100
28 Ld 4x4 TQFN
L28.4x4
ISL62881BHRTZ*
62881B HRTZ
-10 to +100
32 Ld 5x5 TQFN
L32.5x5E
NOTES:
1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL62881, ISL62881B. For more information on
MSL please see techbrief TB363.
October 26, 2009
FN6924.0
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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Pin Configurations
ISL62881
(28 LD TQFN)
TOP VIEW
ISL62881, ISL62881B
ISL62881B
(32 LD TQFN)
TOP VIEW
28 27 26 25 24 23 22
CLK_EN# 1
PGOOD 2
RBIAS 3
VW 4
COMP 5
FB 6
VSEN 7
GND PAD
(BOTTOM)
21 VID1
20 VID0
19 VCCP
18 LGATE
17 VSSP
16 PHASE
15 UGATE
8 9 10 11 12 13 14
32 31 30 29 28 27 26 25
PGOOD 1
RBIAS 2
VR_TT# 3
NTC 4
GND 5
VW 6
COMP 7
FB 8
GND PAD
(BOTTOM)
24 VID1
23 VID0
22 VCCP
21 LGATEb
20 LGATEa
19 VSSP
18 PHASE
17 UGATE
9 10 11 12 13 14 15 16
Pin Function Description
GND (Bottom Pad)
Signal common of the IC. Unless otherwise stated,
signals are referenced to the GND pin.
CLK_EN#
Open drain output to enable system PLL clock; goes
active 13 switching cycles after Vcore is within 10% of
Vboot.
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Power-Good open-drain output indicating when the
regulator is able to supply regulated voltage. Pull-up
externally with a 680Ω resistor to VCCP or 1.9kΩ to 3.3V.
RBIAS
A resistor to GND sets internal current reference. A
147kΩ resistor sets the controller for CPU core
application and a 47kΩ resistor sets the controller for
GPU core application.
VR_TT#
Thermal overload output indicator.
NTC
Thermistor input to VR_TT# circuit.
VW
A resistor from this pin to COMP programs the switching
frequency (8kΩ gives approximately 300kHz).
COMP
This pin is the output of the error amplifier. Also, a
resistor across this pin and GND adjusts the overcurrent
threshold.
FB
This pin is the inverting input of the error amplifier.
VSEN
Remote core voltage sense input. Connect to
microprocessor die.
RTN
Remote voltage sensing return. Connect to ground at
microprocessor die.
ISUM- and ISUM+
Droop current sense input.
VDD
5V bias power.
VIN
Battery supply voltage, used for feed-forward.
IMON
An analog output. IMON outputs a current proportional to
the regulator output current.
BOOT
Connect an MLCC capacitor across the BOOT and the
PHASE pins. The boot capacitor is charged through an
internal boot diode connected from the VCCP pin to the
BOOT pin, each time the PHASE pin drops below VCCP
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ISL62881, ISL62881B
minus the voltage dropped across the internal boot
diode.
UGATE
Output of the high-side MOSFET gate driver. Connect the
UGATE pin to the gate of the high-side MOSFET.
PHASE
Current return path for the high-side MOSFET gate
driver. Connect the PHASE pin to the node consisting of
the high-side MOSFET source, the low-side MOSFET drain
and the output inductor.
VSSP
Current return path for the low-side MOSFET gate driver.
Connect the VSSP pin to the source of the low-side
MOSFET through a low impedance path, preferably in
parallel with the trace connecting the LGATE pin to the
gate of the low-side MOSFET.
LGATE (For ISL62881)
Output of the low-side MOSFET gate driver. Connect the
LGATE pin to the gate of the low-side MOSFET.
LGATEa (For ISL62881B)
Output of the low-side MOSFET gate driver that is always
active. Connect the LGATEa pin to the gate of the low-
side MOSFET that is active all the time.
LGATEb (For ISL62881B)
Another output of the low-side MOSFET gate driver. This
gate driver will be pulled low when the DPRSLPVR pin
logic is high. Connect the LGATEb pin to the gate of the
low-side MOSFET that is idle in deeper sleep mode.
VCCP
Input voltage bias for the internal gate drivers. Connect
+5V to the VCCP pin. Decouple with at least 1µF of an
MLCC capacitor to VSSP1 and VSSP2 pins respectively.
VID0, VID1, VID2, VID3, VID4, VID5, VID6
VID input with VID0 = LSB and VID6 = MSB.
VR_ON
Voltage regulator enable input. A high level logic signal
on this pin enables the regulator.
DPRSLPVR
A high level logic signal on this pin puts the ISL62881 in
1-phase diode emulation mode. If RBIAS = 47kΩ (GPU
VR application), this pin also controls Vcore slew rate.
Vcore slews at 5mV/µs for DPRSLPVR = 0 and 10mV/µs
for DPRSLPVR = 1. If RBIAS = 147kΩ (CPU VR
application), this pin doesn’t control Vcore slew rate.
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ISL62881, ISL62881B
Block Diagram
VIN VSEN
PGOOD CLK_EN#
VDD
VR_ON
DPRSLPVR
RBIAS
VID0
VID1
VID2
VID3
VID4
VID5
VID6
RTN
FB
COMP
VW
IMON
ISUM+
ISUM-
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MODE
CONTROL
DAC
AND
SOFT
START
PGOOD
AND
CLK_EN#
LOGIC
6µA 54µA 1.20V
1.24V
PROTECTION FLT
WOC OC
VIN
CLOCK
VDAC
COMP
VW
ISL62881B
ONLY
VR_TT#
NTC
Σ
E/A
Idroop
Imon
CURRENT
SENSE
2.5
X
VIN VDAC
MODULATOR
WOC
COMP
CURRENT
COMPARATORS
60µA
OC
Σ
DRIVER
SHOOT
THROUGH
PROTECTION
DRIVER
DRIVER
BOOT
UGATE
PHASE
VCCP
LGATEA
VSSP
ISL62881 ONLY
LGATEB
ADJ. OCP
THRESHOLD
COMP
ISL62881B
ONLY
GND
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ISL62881, ISL62881B
Absolute Maximum Ratings
Supply Voltage, VDD. . . . . . . . . . . . . . . . . . . .-0.3V to +7V
Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . +28V
Boot Voltage (BOOT) . . . . . . . . . . . . . . . . . . -0.3V to +33V
Boot to Phase Voltage (BOOT-PHASE) . . . . -0.3V to +7V(DC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +9V(<10ns)
Phase Voltage (PHASE) . . . . . -7V (<20ns Pulse Width, 10µJ)
UGATE Voltage (UGATE) . . . . . . . PHASE-0.3V (DC) to BOOT
. . . . . . . . . PHASE-5V (<20ns Pulse Width, 10µJ) to BOOT
LGATE Voltage (LGATE) . . . . . . . . -0.3V (DC) to VDD + 0.3V
. . . . . . . . . -2.5V (<20ns Pulse Width, 5µJ) to VDD + 0.3V
All Other Pins. . . . . . . . . . . . . . . . . . -0.3V to (VDD + 0.3V)
Open Drain Outputs, PGOOD, VR_TT#, CLK_EN#
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +7V
Thermal Information
Thermal Resistance (Typical, Notes 4, 5)θJA (°C/W) θJC (°C/W)
28 Ld TQFN Package. . . . . . . . . . .
40
3
32 Ld TQFN Package. . . . . . . . . . .
32
3
Maximum Junction Temperature . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . +5V to 25V
Ambient Temperature . . . . . . . . . . . . . . . -10°C to +100°C
Junction Temperature . . . . . . . . . . . . . . . -10°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
features. See Tech Brief TB379.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Operating Conditions: VDD = 5V, TA = -10°C to +100°C, fSW = 300kHz, unless otherwise
noted. Boldface limits apply over the operating temperature range, -10°C to
+100°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
(Note 7) TYP (Note 7) UNITS
INPUT POWER SUPPLY
+5V Supply Current
IVDD
VR_ON = 1V
VR_ON = 0V
3.2 4.0
1
mA
µA
Battery Supply Current
IVIN
VR_ON = 0V
VIN Input Resistance
RVIN
VR_ON = 1V
Power-On-Reset Threshold
PORr
VDD rising
PORf
VDD falling
SYSTEM AND REFERENCES
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System Accuracy
%Error (VCC_CORE) No load; closed loop, active mode range
VID = 0.75V to 1.50V
4.00
900
4.35
4.15
1
4.5
-0.5
+0.5
µA
kΩ
V
V
%
VID = 0.5V to 0.7375V
-8 +8 mV
VID = 0.3V to 0.4875V
-15
+15
mV
VBOOT
Maximum Output Voltage
Minimum Output Voltage
(Note 6)
VCC_CORE(max)
VCC_CORE(min)
VID = [0000000]
VID = [1111111]
1.0945 1.100 1.1055
1.500
0
V
V
V
RBIAS Voltage
CHANNEL FREQUENCY
RBIAS = 147kΩ
1.45 1.47 1.49
V
Nominal Channel Frequency
Adjustment Range
fSW(nom)
RFSET = 7kΩ, VCOMP = 1V
295 310 325
200
500
kHz
kHz
AMPLIFIERS
Current-Sense Amplifier
Input Offset
IFB = 0A
-0.15
+0.15 mV
Error Amp DC Gain (Note 6)
Error Amp Gain-Bandwidth
Product (Note 6)
Av0
GBW
CL = 20pF
90 dB
18 MHz
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