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ispClock5300S Family
In-System Programmable, Zero-Delay
Universal Fan-Out Buffer, Single-Ended
October 2007
Preliminary Data Sheet DS1010
Features
Four Operating Configurations
• Zero delay buffer
• Zero delay and non-zero delay buffer
• Dual non-zero delay buffer
• Non-zero delay buffer with output divider
8MHz to 267MHz Input/Output Operation
Low Output to Output Skew (<100ps)
Low Jitter Peak-to-Peak (< 70 ps)
Up to 20 Programmable Fan-out Buffers
• Programmable single-ended output standards
and individual enable controls
- LVTTL, LVCMOS, HSTL, eHSTL, SSTL
• Programmable output impedance
- 40 to 70Ω in 5Ω increments
• Programmable slew rate
• Up to 10 banks with individual VCCO and GND
- 1.5V, 1.8V, 2.5V, 3.3V
Fully Integrated High-Performance PLL
• Programmable lock detect
• Three “Power of 2” output dividers (5-bit)
• Programmable on-chip loop filter
• Compatible with spread spectrum clocks
• Internal/external feedback
Precision Programmable Phase Adjustment
www.DataSh(eSekt4eUw.co)mPer Output
• 8 settings; minimum step size 156ps
- Locked to VCO frequency
• Up to +/- 5ns skew range
• Coarse and fine adjustment modes
Up to Three Clock Frequency Domains
Flexible Clock Reference and External
Feedback Inputs
• Programmable single-ended or differential input
reference standards
- LVTTL, LVCMOS, SSTL, HSTL, LVDS,
LVPECL, Differential HSTL, Differential
SSTL
• Clock A/B selection multiplexer
• Programmable Feedback Standards
- LVTTL, LVCMOS, SSTL, HSTL
• Programmable termination
All Inputs and Outputs are Hot Socket
Compliant
Full JTAG Boundary Scan Test In-System
Programming Support
Exceptional Power Supply Noise Immunity
Commercial (0 to 70°C) and Industrial
(-40 to 85°C) Temperature Ranges
48-pin and 64-pin TQFP Packages
Applications
• Circuit board common clock distribution
• PLL-based frequency generation
• High fan-out clock buffer
• Zero-delay clock buffer
ispClock5300S Family Functional Diagram
LOCK
PLL_ BYPASS
REFA /
REFP
REFB /
REFN
REFSEL
FBK
+
0
1
PHASE
FREQ.
DETECT
LOOP
FILTER
VCO
OUTPUT
DIVIDERS
1 V0
0 5-Bit
SKEW
OUTPUT
CONTROL DRIVERS
OUTPUT 1
V1
5-bit
V2
5-bit
OUTPUT
ROUTING
MATRIX
OUTPUT N
© 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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1
DS1010_01.4

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Lattice Semiconductor
ispClock5300S Family Data Sheet
General Description
The ispClock5300S is an in-system-programmable zero delay universal fan-out buffer for use in clock distribution
applications. The ispClock5312S, the first member of the ispClock5300S family, provides up to 12 single-ended
ultra low skew outputs. Each pair of outputs may be independently configured to support separate I/O standards
(LVTTL, LVCMOS -3.3V, 2.5V, 1.8, SSTL, HSTL) and output frequency. In addition, each output provides indepen-
dent programmable control of termination, slew-rate, and timing skew. All configuration information is stored on-
chip in non-volatile E2CMOS® memory.
The ispClock5300S devices provide extremely low propagation delay (zero-delay) from input to output using the
on-chip low jitter high-performance PLL. A set of three programmable 5-bit counters can be used to generate three
frequencies derived from the PLL clock. These counters are programmable in powers of 2 only (1, 2, 4, 8, 16, 32).
The clock output from any of the V-dividers can then be routed to any clock output pin through the output routing
matrix. The output routing matrix, in addition, also enables routing of reference clock inputs directly to any output.
The ispClock5300S device can be configured to operate in four modes: zero delay buffer mode, dual non-zero
delay buffer mode, non-zero delay buffer mode with output dividers, and combined zero-delay and non-zero delay
buffer mode.
The core functions of all members of the ispClock5300S family are identical. Table 1 summarizes the
ispClock5300S device family.
Table 1. ispClock5300S Family
Device
ispClock5320S
ispClock5316S
ispClock5312S
ispClock5308S
ispClock5304S
Number of Programmable
Clock Inputs
1 Differential, 2 Single-Ended
1 Differential, 2 Single-Ended
1 Differential, 2 Single-Ended
1 Differential, 2 Single-Ended
1 Differential, 2 Single-Ended
Number of Programmable
Single-Ended Outputs
20
16
12
8
4
Figure 1. ispClock5304S Functional Block Diagram
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VTT_REFA
VTT_REFB
REFA_REFP
REFB_REFN
REFSEL
+
0
1
LOCK
RESET
LOCK
DETECT
PHASE
DETECT
LOOP
FILTER
VCO
FBK
VTT_FBK
PLL_ BYPASS OEX OEY
OUTPUT ENABLE
CONTROLS
OUTPUT ROUTING
MATRIX
SKEW
OUTPUT
CONTROL DRIVERS
OUTPUT
DIVIDERS
1 V0
0 5-bit
BANK_0A
BANK_0B
BANK_1A
V1 BANK_1B
5-bit
SKEW
OUTPUT
V2 CONTROL DRIVERS
5-bit
JTAG INTERFACE
TDI TMS TCK TDO
2

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Lattice Semiconductor
ispClock5300S Family Data Sheet
Figure 2. ispClock5308S Functional Block Diagram
LOCK
RESET
PLL_ BYPASS OEX OEY
VTT_REFA
VTT_REFB
REFA_REFP
REFB_REFN
REFSEL
FBK
VTT_FBK
+
0
1
LOCK
DETECT
PHASE
DETECT
LOOP
FILTER
VCO
OUTPUT ENABLE
CONTROLS
OUTPUT ROUTING
SKEW
OUTPUT
MATRIX
CONTROL DRIVERS
OUTPUT
DIVIDERS
BANK_0A
1 V0
BANK_0B
0 5-bit
BANK_1A
BANK_1B
V1
5-bit BANK_2A
BANK_2B
V2
5-bit BANK_3A
BANK_3B
SKEW
CONTROL
OUTPUT
DRIVERS
JTAG INTERFACE
TDI TMS TCK TDO
Figure 3. ispClock5312S Functional Block Diagram
LOCK
RESET
PLL_ BYPASS OEX OEY
VTT_REFA
VTT_REFB
REFA_REFP
REFB_REFN
REFSEL
FBK
VTT_FBK
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+
0
1
LOCK
DETECT
PHASE
DETECT
LOOP
FILTER
VCO
JTAG INTERFACE
OUTPUT ENABLE
CONTROLS
OUTPUT ROUTING
SKEW
OUTPUT
MATRIX
CONTROL DRIVERS
OUTPUT
DIVIDERS
BANK_0A
1 V0
BANK_0B
0 5-bit
BANK_1A
BANK_1B
V1
5-bit BANK_2A
BANK_2B
V2
5-bit
SKEW
CONTROL
OUTPUT
DRIVERS
BANK_3A
BANK_3B
BANK_4A
BANK_4B
BANK_5A
BANK_5B
TDI TMS TCK TDO
3

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Lattice Semiconductor
ispClock5300S Family Data Sheet
Figure 4. ispClock5316S Functional Block Diagram
LOCK
RESET
PLL_ BYPASS OEX OEY
VTT_REFA
VTT_REFB
REFA_REFP
REFB_REFN
REFSEL
FBK
VTT_FBK
0
1
LOCK
DETECT
PHASE
DETECT
LOOP
FILTER
VCO
JTAG INTERFACE
TDI TMS TCK TDO
OUTPUT ENABLE
CONTROLS
OUTPUT ROUTING
SKEW
OUTPUT
MATRIX
CONTROL DRIVERS
OUTPUT
DIVIDERS
BANK _0 A
1 V0
BANK _0 B
0 5-bit
BANK _1 A
BANK _1 B
V1
5-bit BANK _2 A
BANK _2 B
V2
5-bit BANK _3 A
SKEW
CONTROL
OUTPUT
DRIVERS
BANK _3 B
BANK _4 A
BANK _4 B
BANK _5 A
BANK _5 B
BANK _6 A
BANK _6 B
BANK _7 A
BANK _7 B
Figure 5. ispClock5320S Functional Block Diagram
LOCK
RESET
PLL_ BYPASS OEX OEY
VTT_REFA
VTT_REFB
REFA_REFP
REFB_REFN
REFSEL
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FBK
VTT_FBK
0
1
LOCK
DETECT
PHASE
DETECT
LOOP
FILTER
VCO
JTAG INTERFACE
OUTPUT ENABLE
CONTROLS
OUTPUT ROUTING
SKEW
OUTPUT
MATRIX
CONTROL DRIVERS
OUTPUT
DIVIDERS
BANK_0A
1 V0
BANK_0B
0 5-bit
BANK_1A
BANK_1B
V1
5-bit BANK_2A
BANK_2B
V2
5-bit BANK_3A
SKEW
CONTROL
OUTPUT
DRIVERS
BANK_3B
BANK_4A
BANK_4B
BANK_5A
BANK_5B
BANK_6A
BANK_6B
BANK_7A
BANK_7B
BANK_8A
BANK_8B
BANK_9A
BANK_9B
TDI TMS TCK TDO
4

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Lattice Semiconductor
ispClock5300S Family Data Sheet
Absolute Maximum Ratings
ispClock5300S
Core Supply Voltage VCCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V
PLL Supply Voltage VCCA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V
JTAG Supply Voltage VCCJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V
Output Driver Supply Voltage VCCO . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V
Output Voltage1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150°C
Junction Temperature with power supplied . . . . . . . . . . . . . . . . . . . -40 to 130°C
1. When applied to an output when in high-Z condition
Recommended Operating Conditions
Symbol
Parameter
Conditions
VCCD
VCCJ
VCCA
VCCXSLEW
TJOP
Core Supply Voltage
JTAG I/O Supply Voltage
Analog Supply Voltage
VCC Turn-on Ramp Rate
Operating Junction Temperature
All supply pins
Commercial
Industrial
Commercial
TA
Ambient Operating Temperature
Industrial
1. Device power dissipation may also limit maximum ambient operating temperature.
ispClock5300S
Min.
Max.
3.0 3.6
1.62 3.6
3.0 3.6
— 0.33
0 120
-40 130
0 701
-40 851
Units
V
V
V
V/µs
°C
°C
Recommended
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Operating
Conditions
VCCO
vs.
Logic
Standard
Logic Standard
VCCO (V)
Min.
Typ.
Max.
VREF (V)
Min.
Typ.
Max.
Min.
VTT (V)
Typ.
Max.
LVTTL
3.0 3.3 3.6
LVCMOS 1.8V
1.71 1.8 1.89
LVCMOS 2.5V
2.375 2.5 2.625
LVCMOS 3.3V
3.0 3.3 3.6
SSTL1.8
1.71 1.8 1.89 0.84
SSTL2 Class 1
2.375 2.5 2.625 1.15
SSTL3 Class 1
3.0 3.3 3.6 1.30
HSTL Class 1
1.425 1.5 1.575 0.68
eHSTL Class 1
1.71 1.8 1.89 0.84
Note: ‘—’ denotes VREF or VTT not applicable to this logic standard
0.90
1.25
1.50
0.75
0.90
0.95
1.35
1.70
0.90
0.95
— 0.5 x VCCO
VREF - 0.04 VREF VREF + 0.04
VREF - 0.05 VREF VREF + 0.05
— 0.5 x VCCO
— 0.5 x VCCO
5