IS61WV12816DALL.pdf 데이터시트 (총 21 페이지) - 파일 다운로드 IS61WV12816DALL 데이타시트 다운로드

No Preview Available !

IS61WV12816DALL/DALS
IS61WV12816DBLL/DBLS
IS64WV12816DBLL/DBLS
www.DataSheet4U.com
128K x 16 HIGH SPEED ASYNCHRONOUS
CMOS STATIC RAM
MAY 2008
FEATURES
HIGH SPEED: (IS61/64WV12816DALL/DBLL)
• High-speed access time: 8, 10, 12, 20 ns
• Low Active Power: 135 mW (typical)
• Low Standby Power: 12 μW (typical)
CMOS standby
LOW POWER: (IS61/64WV12816DALS/DBLS)
• High-speed access time: 25, 35 ns
• Low Active Power: 55 mW (typical)
• Low Standby Power: 12 μW (typical)
CMOS standby
• Single power supply
— VDD 1.65V to 2.2V (IS61WV12816DAxx)
— VDD 2.4V to 3.6V (IS61/64WV12816DBxx)
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial and Automotive temperature support
• Lead-free available
DESCRIPTION
The ISSI IS61WV12816DAxx/DBxx and IS64WV12816DBxx
are high-speed, 2,097,152-bit static RAMs organized as
131,072 words by 16 bits. It is fabricated using ISSI's high-
performance CMOS technology. This highly reliable pro-
cess coupled with innovative circuit design techniques,
yields high-performance and low power consumption de-
vices.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
The IS61WV12816DAxx/DBxx and IS64WV12816DBxx are
packaged in the JEDEC standard 44-pin TSOP Type II and
48-pin Mini BGA (6mm x 8mm).
FUNCTIONAL BLOCK DIAGRAM
A0-A16
DECODER
128K x 16
MEMORY ARRAY
VDD
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
I/O
DATA
CIRCUIT
COLUMN I/O
CE
OE
WE
CONTROL
CIRCUIT
UB
LB
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
05/01/08
1

No Preview Available !

IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS,
IS64WV12816DBLL/DBLS
www.DataSheet4U.com
TRUTH TABLE
Mode
WE CE OE LB UB
Not Selected
XHXXX
Output Disabled H L H X X
X LXHH
Read
HL L LH
HL LHL
HL L L L
Write
L LXLH
L LXHL
L LXL L
I/O PIN
I/O0-I/O7 I/O8-I/O15
High-Z
High-Z
High-Z
DOUT
High-Z
DOUT
DIN
High-Z
DIN
High-Z
High-Z
High-Z
High-Z
DOUT
DOUT
High-Z
DIN
DIN
VDD Current
ISB1, ISB2
ICC
ICC
ICC
PIN CONFIGURATION
44-Pin TSOP (Type II) (T)
A4 1
A3 2
A2 3
A1 4
A0 5
CE 6
I/O0 7
I/O1 8
I/O2 9
I/O3 10
VDD 11
GND 12
I/O4 13
I/O5 14
I/O6 15
I/O7 16
WE 17
A16 18
A15 19
A14 20
A13 21
A12 22
44 A5
43 A6
42 A7
41 OE
40 UB
39 LB
38 I/O15
37 I/O14
36 I/O13
35 I/O12
34 GND
33 VDD
32 I/O11
31 I/O10
30 I/O9
29 I/O8
28 NC
27 A8
26 A9
25 A10
24 A11
23 NC
PIN DESCRIPTIONS
A0-A16
I/O0-I/O15
CE
OE
WE
LB
UB
NC
VDD
GND
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
Lower-byte Control (I/O0-I/O7)
Upper-byte Control (I/O8-I/O15)
No Connection
Power
Ground
2 Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
05/01/08

No Preview Available !

IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS,
IS64WV12816DBLL/DBLS
www.DataSheet4U.com
PIN CONFIGURATION
48-Pin mini BGA (B)
1 23 45 6
A LB OE A0 A1 A2 NC
B
I/O8
UB
A3
A4 CE I/O0
C I/O9 I/O10 A5
A6 I/O1 I/O2
D GND I/O11 NC
A7
I/O3
VDD
E VDD I/O12
NC
A16 I/O4 GND
F I/O14 I/O13 A14 A15 I/O5 I/O6
G I/O15 NC A12 A13 WE I/O7
H
NC A8
A9 A10 A11 NC
PIN DESCRIPTIONS
A0-A16
I/O0-I/O15
CE
OE
WE
LB
UB
NC
VDD
GND
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
Lower-byte Control (I/O0-I/O7)
Upper-byte Control (I/O8-I/O15)
No Connection
Power
Ground
1
2
3
4
5
6
7
8
9
10
11
12
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
05/01/08
3

No Preview Available !

IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS,
IS64WV12816DBLL/DBLS
www.DataSheet4U.com
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 3.3V + 5%
Symbol Parameter
Test Conditions
Min.
VOH Output HIGH Voltage
VDD = Min., IOH = –4.0 mA
2.4
VOL Output LOW Voltage
VDD = Min., IOL = 8.0 mA
VIH Input HIGH Voltage
VIL Input LOW Voltage(1)
2
–0.3
ILI Input Leakage
GND VIN VDD
–1
ILO Output Leakage
GND VOUT VDD, Outputs Disabled
–1
Note:
1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested.
VIH (max.) = VDD + 0.3V DC; VIH (max.) = VDD + 2.0V AC (pulse width < 10 ns). Not 100% tested.
Max.
0.4
VDD + 0.3
0.8
1
1
Unit
V
V
V
V
µA
µA
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 2.4V-3.6V
Symbol Parameter
Test Conditions
Min.
VOH Output HIGH Voltage
VDD = Min., IOH = –1.0 mA
1.8
VOL Output LOW Voltage
VDD = Min., IOL = 1.0 mA
VIH Input HIGH Voltage
2.0
VIL Input LOW Voltage(1)
–0.3
ILI Input Leakage
GND VIN VDD
–1
ILO Output Leakage
GND VOUT VDD, Outputs Disabled
–1
Note:
1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested.
VIH (max.) = VDD + 0.3V DC; VIH (max.) = VDD + 2.0V AC (pulse width < 10 ns). Not 100% tested.
Max.
0.4
VDD + 0.3
0.8
1
1
Unit
V
V
V
V
µA
µA
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 1.65V-2.2V
Symbol Parameter
Test Conditions VDD Min.
VOH
Output HIGH Voltage
IOH = -0.1 mA
1.65-2.2V
1.4
VOL
Output LOW Voltage
IOL = 0.1 mA
1.65-2.2V
VIH Input HIGH Voltage
1.65-2.2V
1.4
VIL(1)
Input LOW Voltage
1.65-2.2V
–0.2
ILI Input Leakage
GND VIN VDD
–1
ILO Output Leakage
GND VOUT VDD, Outputs Disabled
–1
Note:
1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested.
VIH (max.) = VDD + 0.3V DC; VIH (max.) = VDD + 2.0V AC (pulse width < 10 ns). Not 100% tested.
Max.
0.2
VDD + 0.2
0.4
1
1
Unit
V
V
V
V
µA
µA
4 Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
05/01/08

No Preview Available !

IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS,
IS64WV12816DBLL/DBLS
www.DataSheet4U.com
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level (VRef)
OutputLoad
R1 ( Ω )
R2 ( Ω )
VTM (V)
Unit
(2.4V-3.6V)
0.4V to VDD - 0.3V
1V/ ns
VDD /2
See Figures 1 and 2
1909
1105
3.0V
Unit
(3.3V + 5%)
0.4V to VDD - 0.3V
1V/ ns
VDD + 0.05
2
See Figures 1 and 2
317
351
3.3V
Unit
(1.65V-2.2V)
0.4V to VDD - 0.3V
1V/ ns
0.9V
See Figures 1 and 2
13500
10800
1.8V
AC TEST LOADS
OUTPUT
ZO = 50Ω
50Ω
VDD/2
30 pF
Including
jig and
scope
Figure 1.
VTM
R1
OUTPUT
5 pF
Including
jig and
scope
Figure 2.
R2
1
2
3
4
5
6
7
8
9
10
11
12
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
05/01/08
5