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DESCRIPTION
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Low Profile Registered DDR SDRAM DIMM
HYMD212G726A(L)S4M-M/K/H/L
Preliminary
Hynix HYMD212G726A(L)S4M-M/K/H/L series is Low Profile registered 184-pin double data rate Synchronous DRAM
Dual In-Line Memory Modules (DIMMs) which are organized as 128Mx72 high-speed memory arrays. Hynix
HYMD212G726A(L)S4M-M/K/H/L series consists of eighteen stacked 128Mx4 DDR SDRAM in 400mil TSOP II packages
on a 184pin glass-epoxy substrate. Hynix HYMD212G726A(L)S4M-M/K/H/L series provide a high performance 8-byte
interface in 5.25" width form factor of industry standard. It is suitable for easy interchange and addition.
Hynix HYMD212G726A(L)S4M-M/K/H/L series is designed for high speed of up to 133MHz and offers fully synchronous
operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control
inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on
both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high
bandwidth. All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable
latencies and burst lengths allow variety of device operation in high performance memory system.
Hynix HYMD212G726A(L)S4M-M/K/H/L series incorporates SPD(serial presence detect). Serial presence detect func-
tion is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to
identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
FEATURES
• 1GB (128M x 72) Low Profile Registered DDR DIMM
based on stacked 128Mx4 DDR SDRAM
• JEDEC Standard 184-pin dual in-line memory module
(DIMM)
• Error Check Correction (ECC) Capability
• Registered inputs with one-clock delay
• Phase-lock loop (PLL) clock driver to reduce loading
• 2.5V +/- 0.2V VDD and VDDQ Power supply
• All inputs and outputs are compatible with SSTL_2
interface
• Fully differential clock operations (CK & /CK) with
100MHz/125MHz/133MHz
• Programmable CAS Latency 2 / 2.5 supported
• Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
• tRAS Lock-out function supported
• Internal four bank operations with single pulsed RAS
• Auto refresh and self refresh supported
• 8192 refresh cycles / 64ms
ORDERING INFORMATION
Part No.
HYMD212G726A(L)S4M-M
HYMD212G726A(L)S4M-K
HYMD212G726A(L)S4M-H
HYMD212G726A(L)S4M-L
Power Supply
Clock Frequency
VDD=2.5V
VDDQ=2.5V
133MHz (*DDR266:2-2-2)
133MHz (*DDR266A)
133MHz (*DDR266B)
100MHz (*DDR200)
Interface
Form Factor
SSTL_2
184pin Low Profile Registered
DIMM
5.25 x 1.2 x 0.15 inch
* JEDEC Defined Specifications compliant
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.2/May. 02
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HYMD212G726A(L)S4M-M/K/H/L
PIN DESCRIPTION
Pin
CK0, /CK0
CS0
CKE0
/RAS, /CAS, /WE
A0 ~ A12
BA0, BA1
DQ0~DQ63
CB0~CB7
DQS0~DQS17
DM0~DM8
VDD
/RESET
Pin Description
Differential Clock Inputs
Chip Select Input
Clock Enable Input
Commend Sets Inputs
Address
Bank Address
Data Inputs/Outputs
Data Strobe Inputs/Outputs
Data Strobe Inputs/Outputs
Data-in Mask
Power Supply
Reset Enable
Pin
VDDQ
VSS
VREF
VDDSPD
SA0~SA2
SCL
SDA
WP
VDDID
DU
NC
FETEN
Pin Description
DQs Power Supply
Ground
Reference Power Supply
Power Supply for SPD
E2PROM Address Inputs
E2PROM Clock
E2PROM Data I/O
Write Protect Flag
VDD Identification Flag
Do not Use
No Connection
FET Enable
PIN ASSIGNMENT
Pin Name Pin Name Pin Name Pin Name Pin Name Pin
Name
1
VREF
32
A5
62 VDDQ
93
VSS 124 VSS 154
/RAS
2
DQ0
33 DQ24 63
/WE
94
DQ4
125
A6
155 DQ45
3
VSS 34 VSS 64 DQ41 95
DQ5
126 DQ28 156
VDDQ
4
DQ1
35 DQ25 65
/CAS
96
VDDQ
127
DQ29
157
/CS0
5 DQS0 36 DQS3 66 VSS
97 DQS9 128 VDDQ 158
/CS1*
6
DQ2
37
A4
67 DQS5 98
DQ6
129 DQS12 159
DM5
7
VDD
38
VDD
68 DQ42
99
DQ7
130
A3
160
VSS
8
DQ3
39 DQ26 69 DQ43 100
VSS
131 DQ30 161
DQ46
9
NC
40 DQ27 70
VDD
101
NC
132 VSS 162 DQ47
10 /RESET 41 A2 71 NC 102 NC 133 DQ31 163
NC
11 VSS 42 Vss 72 DQ48 103 A13* 134 CB4 164 VDDQ
12 DQ8 43 A1 73 DQ49 104 VDDQ 135 CB5 165 DQ52
13 DQ9 44 CB0 74 VSS 105 DQ12 136 VDDQ 166 DQ53
14 DQS1 45
CB1
75
DU
106 DQ13 137
CK0
167 NC, FETEN*
15 VDDQ 46
VDD
76
DU
107 DQS10 138
/CK0
168
VDD
16
DU
47
DQS8
77
VDDQ
108
VDD
139
VSS
169
DM6
17
DU
48
A0
78 DQS6 109 DQ14 140 DQS17 170
DQ54
18 VSS 49 CB2 79 DQ50 110 DQ15 141 A10 171 DQ55
19 DQ10 50 VSS 80 DQ51 111 CKE1* 142 CB6 172 VDDQ
20 DQ11 51 CB3 81 VSS 112 VDDQ 143 VDDQ 173
NC
21 CKE0 52
BA1
82 VDDID 113
BA2*
144
CB7
174
DQ60
22 VDDQ Key 83 DQ56 114 DQ20 key 175 DQ61
23 DQ16 53 DQ32 84 DQ57 115 A12 145 VSS 176
VSS
24
DQ17
54
VDDQ
85
VDD
116
VSS
146 DQ36 177
DM7
25 DQS2 55 DQ33 86 DQS7 117 DQ21 147 DQ37 178
DQ62
26 VSS 56 DQS4 87 DQ58 118 A11 148 VDD 179 DQ63
27
A9
57 DQ34 88 DQ59 119 DQS11 149 DQS13 180
VDDQ
28 DQ18 58 VSS 89 VSS 120 VDD 150 DQ38 181
SA0
29 A7 59 BA0 90 WP 121 DQ22 151 DQ39 182 SA1
30 VDDQ 60 DQ35 91
SDA
122
A8
152 VSS 183
SA2
31 DQ19 61 DQ40 92 SCL 123 DQ23 153 DQ44 184 VDDSPD
* These are not used on this module but may be used for other module in 184pin DIMM family
Rev. 0.2/May. 02
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HYMD212G726A(L)S4M-M/K/H/L
FUNCTIONAL BLOCK DIAGRAM
Vss
/RCS1
/RCS0
DQS0
DQ0
DQ1
DQ2
DQ3
DQS1
DQ8
DQ9
DQ10
DQ11
DQS2
DQ16
DQ17
DQ18
DQ19
DQS3
DQ24
DQ25
DQ26
DQ27
DQS4
DQ32
DQ33
DQ34
DQ35
DQS5
DQ40
DQ41
DQ42
DQ43
DQS6
DQ48
DQ49
DQ50
DQ51
DQS7
DQ56
DQ57
DQ58
DQ59
DQS8
CB0
CB1
CB2
CB3
DQS /CS DM
I/O 0
I/O 1
I/O 2
D0
I/O 3
DQS /CS DM
I/O 0
I/O 1
I/O 2
D1
I/O 3
DQS /CS DM
I/O 0
I/O 1
I/O 2
D2
I/O 3
DQS /CS DM
I/O 0
I/O 1
I/O 2
D3
I/O 3
DQS /CS DM
I/O 0
I/O 1
I/O 2
D4
I/O 3
DQS /CS DM
I/O 0
I/O 1
I/O 2
D5
I/O 3
DQS /CS DM
I/O 0
I/O 1
I/O 2
D6
I/O 3
DQS /CS DM
I/O 0
I/O 1
I/O 2
D7
I/O 3
DQS /CS DM
I/O 0
I/O 1
I/O 2
D8
I/O 3
SCL
WP
DQS /CS DM
I/O 0
I/O 1
I/O 2
D18
I/O 3
DQS /CS DM
I/O 0
I/O 1
I/O 2
D19
I/O 3
DQS /CS DM
I/O 0
I/O 1
I/O 2
D20
I/O 3
DQS /CS DM
I/O 0
I/O 1
I/O 2
D21
I/O 3
DQS /CS DM
I/O 0
I/O 1
I/O 2
D22
I/O 3
DQS /CS DM
I/O 0
I/O 1
I/O 2
D23
I/O 3
DQS /CS DM
I/O 0
I/O 1
I/O 2
D24
I/O 3
DQS /CS DM
I/O 0
I/O 1
I/O 2
D25
I/O 3
DQS /CS DM
I/O 0
I/O 1
I/O 2
D26
I/O 3
Serial PD
A0 A1 A2
DQS9
DQ4
DQ5
DQ6
DQ7
DQS10
DQ12
DQ13
DQ14
DQ15
DQS11
DQ20
DQ21
DQ22
DQ23
DQS12
DQ28
DQ29
DQ30
DQ31
DQS13
DQ36
DQ37
DQ38
DQ39
DQS14
DQ44
DQ45
DQ46
DQ47
DQS15
DQ52
DQ53
DQ54
DQ55
DQS16
DQ60
DQ61
DQ62
DQ63
DQS17
CB4
CB5
CB6
CB7
SDA
SA0 SA1 SA2
/CS0
/CS1
BA0-BA1
A0-A12
/RAS
/CAS
CKE0
CKE1
/W E
/RCS0 -->/CS0 : SDRAMs D0-D17
/RCS1-->/CS1 : SDRAMs D18 - D35
RBA0-RBA1--> : BA0-BA1:SDRAMs D0-D35
R
RA0 -R A12 -->A0 - A12 : SDRAMs D0 - D35
/RRAS --> /RAS : SDRAMs D0 - D35
E /RCAS --> /CAS : SDRAMs D0 - D35
G RCKE0 --> CKE : SDRAMs D0 - D17
RCKE1 --> CKE : SDRAMs D18-D35
/RWE --> /WE : SDRAMs D0 - D35
PCK
/RESET
/PCK
CK0, /CK0 --------- PLL*
* Wire per clock loading table/wiring diagrams
DQS /CS DM
I/O 0
I/O 1
I/O 2
D9
I/O 3
DQS /CS DM
I/O 0
I/O 1
I/O 2
D27
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
/CS DM
D10
DQS /CS DM
I/O 0
I/O 1
I/O 2
D28
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
/CS DM
D11
DQS /CS DM
I/O 0
I/O 1
I/O 2
D29
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
/CS DM
D12
DQS /CS DM
I/O 0
I/O 1
I/O 2
D30
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
/CS DM
D13
DQS /CS DM
I/O 0
I/O 1
I/O 2
D31
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
/CS DM
D14
DQS /CS DM
I/O 0
I/O 1
I/O 2
D32
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
/CS DM
D15
DQS /CS DM
I/O 0
I/O 1
I/O 2
D33
I/O 3
DQS
I/O 0
I/O 1
I/O 2
I/O 3
/CS DM
D16
DQS /CS DM
I/O 0
I/O 1
I/O 2
D34
I/O 3
DQS /CS DM
DQS /CS DM
I/O 0
I/O 0
I/O 1
I/O 2
D17
I/O 3
.VDDSPD
.VDDQ
.VDD
.VREF
==
. . . . .VSS
. .VDDID
Notes:
I/O 1
I/O 2
I/O 3
D35
SPD
= D0 - D17
D0 - D17
D0 - D17
=
D0 - D17
Strap:see Note 4
1. DQ-to-I/O wiring may be changed within a byte
2. DQ/DQS/DM/CKE/CS relationships must be
maintained as shown.
3. DQ/DQS resistors should be 18 Ohms.
4. VDDID strap connections(for memory device VDD, VDDQ);
Strap out :(open) : VDD=VDDQ
Strap In (Vss) : VDD=VDDQ
5. Address and control resistors should be 22 Ohms
6. Each chip select and CKE pair alternate btw decks for thermal
enhancement.
Rev. 0.2/May. 02
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HYMD212G726A(L)S4M-M/K/H/L
ABSOLUTE MAXIMUM RATINGS
Parameter
Ambient Temperature
Storage Temperature
Voltage on Any Pin relative to VSS
Voltage on VDD relative to VSS
Voltage on VDDQ relative to VSS
Output Short Circuit Current
Power Dissipation
Soldering Temperature Time
Symbol
TA
TSTG
VIN, VOUT
VDD
VDDQ
IOS
PD
TSOLDER
Rating
0 ~ 70
-55 ~ 125
-0.5 ~ 3.6
-0.5 ~ 3.6
-0.5 ~ 3.6
50
18
260 10
Note : Operation at above absolute maximum rating can adversely affect device reliability
Unit
oC
oC
V
V
V
mA
W
oC Sec
DC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V)
Parameter
Symbol Min Typ.
Power Supply Voltage
VDD
2.3 2.5
Power Supply Voltage
VDDQ
2.3 2.5
Input High Voltage
VIH
VREF + 0.15
-
Input Low Voltage
VIL
-0.3 -
Termination Voltage
VTT
VREF - 0.04
VREF
Reference Voltage
VREF
0.49*VDDQ 0.5*VDDQ
Note :
1. VDDQ must not exceed the level of VDD.
2. VIL (min) is acceptable -1.5V AC pulse width with < 5ns of duration.
3. The value of VREF is approximately equal to 0.5VDDQ.
Max
2.7
2.7
VDDQ + 0.3
VREF - 0.15
VREF + 0.04
0.51*VDDQ
Unit
V
V
V
V
V
V
Note
1
2
3
AC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Min
Max Unit Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
VIH(AC)
VREF + 0.31
V
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
VIL(AC)
VREF - 0.31
V
Input Differential Voltage, CK and /CK inputs
VID(AC)
0.7
VDDQ + 0.6
V
1
Input Crossing Point Voltage, CK and /CK inputs
VIX(AC) 0.5*VDDQ-0.2 0.5*VDDQ+0.2
V
2
Note :
1. VID is the magnitude of the difference between the input level on CK and the input on /CK.
2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.
Rev. 0.2/May. 02
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HYMD212G726A(L)S4M-M/K/H/L
AC OPERATING TEST CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)
Parameter
Reference Voltage
Termination Voltage
AC Input High Level Voltage (VIH, min)
AC Input Low Level Voltage (VIL, max)
Input Timing Measurement Reference Level Voltage
Output Timing Measurement Reference Level Voltage
Input Signal maximum peak swing
Input minimum Signal Slew Rate
Termination Resistor (RT)
Series Resistor (RS)
Output Load Capacitance for Access Time Measurement (CL)
Value
VDDQ x 0.5
VDDQ x 0.5
VREF + 0.31
VREF - 0.31
VREF
VTT
1.5
1
50
25
30
Unit
V
V
V
V
V
V
V
V/ns
pF
Rev. 0.2/May. 02
5