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STB/P432S
Sa mHop Microelectronics C orp.
N-Channel Logic Enhancement Mode Field Effect Transistor
Ver 1.0
PRODUCT SUMMARY
VDSS
ID RDS(ON) (m) Max
9 @ VGS=10V
40V 60A
11 @ VGS=4.5V
FEATURES
Super high dense cell design for extremely low RDS(ON).
High power and current handling capability.
TO-220 & TO-263 package.
D
G
S
S TB S E R IE S
T O -263(DD-P AK )
G
D
S
S TP S E R IE S
TO-220
ABSOLUTE MAXIMUM RATINGS (TC=25°C unless otherwise noted)
Symbol Parameter
VDS Drain-Source Voltage
VGS Gate-Source Voltage
ID Drain Current-Continuous a
TC=25°C
IDM -Pulsed b
EAS Sigle Pulse Avalanche Energy d
PD
Maximum Power Dissipation a
TC=25°C
TJ, TSTG
Operating Junction and Storage
Temperature Range
THERMAL CHARACTERISTICS
R JC
Thermal Resistance, Junction-to-Case
R JA
Thermal Resistance, Junction-to-Ambient
Limit
40
±20
60
240
130
62.5
-55 to 150
2
50
Units
V
V
A
A
mJ
W
°C
°C/W
°C/W
Details are subject to change without notice.
1
Jun,24,2008
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STB/P432S
Ver 1.0
ELECTRICAL CHARACTERISTICS (TC=25°C unless otherwise noted)
4 Symbol Parameter
Conditions
Min
OFF CHARACTERISTICS
BVDSS Drain-Source Breakdown Voltage
VGS=0V , ID=250uA
40
IDSS
Zero Gate Voltage Drain Current
VDS=32V , VGS=0V
IGSS Gate-Body Leakage Current
VGS= ±20V , VDS=0V
ON CHARACTERISTICS
VGS(th)
Gate Threshold Voltage
VDS=VGS , ID=250uA
1
RDS(ON) Drain-Source On-State Resistance
gFS Forward Transconductance
DYNAMIC CHARACTERISTICS c
VGS=10V , ID=30A
VGS=4.5V , ID=28A
VDS=10V , ID=30A
CISS Input Capacitance
COSS
Output Capacitance
CRSS
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS c
VDS=15V,VGS=0V
f=1.0MHz
tD(ON)
tr
tD(OFF)
tf
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
VDD=15V
ID=30A
VGS=10V
RGEN=3.3 ohm
Qg Total Gate Charge
VDS=15V,ID=30A,VGS=10V
VDS=15V,ID=28A,VGS=4.5V
Qgs Gate-Source Charge
VDS=15V,ID=30A,
Qgd Gate-Drain Charge
VGS=10V
DRAIN-SOURCE DIODE CHARACTERISTICS c
IS Maximum Continuous Drain-Source Diode Forward Current
VSD Diode Forward Voltage
VGS=0V,IS=30A
Notes
a.Surface Mounted on FR4 Board,t <_ 10sec.
b.Pulse Test:Pulse Width <_ 300us, Duty Cycle <_ 2%.
c.Guaranteed by design, not subject to production testing.
d.Starting TJ=25°C,L=1.25mH,RG=25,VDD = 20V.(See Figure13)
Typ
1.7
7
9
26
1600
280
150
20
21
45
16
32
15
3.5
7.3
0.95
Max Units
1
±100
V
uA
nA
3V
9 m ohm
11 m ohm
S
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
nC
30 A
1.3 V
Jun,24,2008
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STB/P432S
60
V G S =4 V
50
VGS = 4.5V
40
VGS = 10V
30
20
V G S =3 V
10
VGS = 2.5V
0
0 0.5 1 1.5 2 2.5 3
VDS, Drain-to-Source Voltage(V)
Figure 1. Output Characteristics
20
T j =125 C
15
-55 C
10
25 C
5
Ver 1.0
0
0
0.8 1.6 2.4 3.2 4.0 4.8
VGS, Gate-to-Source Voltage(V)
Figure 2. Transfer Characteristics
15
12
VGS = 4.5V
9
6 VGS = 10V
3
1
1 12 24 36 48 60
ID, Drain Current(A)
Figure 3. On-Resistance vs. Drain Current
and Gate Voltage
2.0
1.8
1.6
V G S =10V
1.4 ID=30A
1.2 V G S =4.5V
ID=28A
1.0
0
0 25 50 75 100 125 150
Tj(°C )
Tj, Junction Temperature(°C )
Figure 4. On-Resistance Variation with Drain
Current and Temperature
1.3
1.2 V DS =V GS
ID=250uA
1.1
1.0
0.9
0.8
0.7
0.6
-50 -25 0 25 50 75 100 125 150
Tj, Junction Temperature(°C )
Figure 5. Gate Threshold Variation
with Temperature
1.15
1.10 ID=250uA
1.05
1.00
0.95
0.90
0.85
-50 -25 0 25 50 75 100 125 150
Tj, Junction Temperature(°C )
Figure 6. Breakdown Voltage Variation
with Temperature
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STB/P432S
30
ID=30A
25
20
75 C
15
125 C
10
5 25 C
0
0 2 4 6 8 10
VGS, Gate-to-Source Voltage(V)
Figure 7. On-Resistance vs.
Gate-Source Voltage
2400
2000
1600
C is s
1200
800
C oss
400
0 C rss
05
10 15
20 25 30
VDS, Drain-to-Source Voltage(V)
Figure 9. Capacitance
Ver 1.0
20.0
10.0
5.0
125 C
75 C
25 C
1.0
0 0.24 0.48 0.72 0.96 1.2
VSD, Body Diode Forward Voltage(V)
Figure 8. Body Diode Forward Voltage
Variation with Source Current
10
VDS =15V
8 ID=30A
6
4
2
0
0 5 10 15 20 25 30 35 40
Qg, Total Gate Charge(nC)
Figure 10. Gate Charge
220
100
60
10
T D(off)
Tr
T D(on)
Tf
V DS =15V ,ID=30A
1 V G S =10V
1 6 10 60 100 300 600
Rg, Gate Resistance()
Figure 11. switching characteristics
1000
100
R DS(ON) Limit
100us
1ms
DC10ms
10
V GS =10V
S ingle P ulse
1 Tc=25 C
0.1 1
10
100
VDS, Drain-Source Voltage(V)
Figure 12. Maximum Safe Operating Area
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STB/P432S
Ver 1.0
15V
VDS
L
RG
20V
tp
D .U .T
IA S
0 .0 1
DR IVE R
+
- VDD
A
Unclamped Inductive Test Circuit
Figure 13a.
V( BR )D S S
tp
IAS
Unclamped Inductive Waveforms
Figure 13b.
2
1
D=0.5
0.2
0.1
0.1 0.05
0.02
0.01
S ingle P uls e
0.01
0.00001
0.0001
0.001
0.01
P DM
t1
t2
1. R JC (t)=r (t) * R JC
2. R JC=S ee Datas heet
3. T JM-T C = P * R JC (t )
4. Duty C ycle, D=t1/t2
0.1 1
Square Wave Pulse Duration (msec)
Figure 14. Normalized Thermal Transient Impedance Curve
10
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