ISL6506B.pdf 데이터시트 (총 8 페이지) - 파일 다운로드 ISL6506B 데이타시트 다운로드

No Preview Available !

®
Data Sheet
ISL6506, ISL6506A, ISL6506B
May 2, 2005
www.DataSheet4U.com
FN9141.2
Multiple Linear Power Controller with
ACPI Control Interface
The ISL6506 complements other power building blocks
(voltage regulators) in ACPI-compliant designs for
microprocessor and computer applications. The IC
integrates the control of the 5VDUAL and 3.3VDUAL rails into
an 8 pin EPAD SOIC package. The ISL6506 operating mode
(active outputs or sleep outputs) is selectable through two
digital control pins, S3# and S5#.
A completely integrated linear regulator generates the
3.3VDUAL voltage plane from the ATX supply’s 5VSB output
during sleep states (S3, S4/S5). In active states (during S0
and S1/S2), the ISL6506 uses an external N-channel pass
MOSFET to connect the outputs directly to the 3.3V input
supplied by an ATX power supply, for minimal losses.
The ISL6506 powers up the 5VDUAL plane by switching in
the ATX 5V output through an NMOS transistor in active
states, or by switching in the ATX 5VSB through a PMOS (or
PNP) transistor in S3 sleep state. In S4/S5 sleep states, the
ISL6506 and ISL6506B 5VDUAL output is shut down. In the
ISL6506A, the 5VDUAL output stays on during S4/S5 sleep
states.
Functionally, the ISL6506 and ISL6506B are identical. The
ISL6506B, however, features a 2A current limit on the
internal 3.3V LDO while the ISL6506 has a 1A current limit.
The ISL6506A has a 1A current limit on the internal 3.3V
LDO.
Ordering Information
TEMP.
PART NUMBER RANGE (°C)
PACKAGE
PKG.
DWG. #
ISL6506CB
0 to 70 8 Ld EPSOIC
M8.15C
ISL6506CBZ (Note) 0 to 70 8 Ld EPSOIC (Pb-free) M8.15C
ISL6506ACB
0 to 70 8 Ld EPSOIC
M8.15C
ISL6506ACBZ (Note) 0 to 70 8 Ld EPSOIC (Pb-free) M8.15C
ISL6506BCB
0 to 70 8 Ld EPSOIC
M8.15C
ISL6506BCBZ (Note) 0 to 70 8 Ld EPSOIC (Pb-free) M8.15C
ISL6506BCBZA
(Note)
0 to 70 8 Ld EPSOIC (Pb-free) M8.15C
*Add “-T” suffix to part number for tape and reel packaging.
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Features
• Provides 2 ACPI-Controlled Voltages
- 5VDUAL USB/Keyboard/Mouse
- 3.3VDUAL/3.3VSB PCI/Auxiliary/LAN
• Excellent 3.3VDUAL Regulation in S3/S4/S5
- ±2.0% over temperature
- 1A Capability on ISL6506 and ISL6506A
- 2A Capability on ISL6506B
• Small Size; Very Low External Component Count
• Over-Temperature Shutdown
• Pb-Free Available (RoHS Compliant)
Applications
ACPI-Compliant Power Regulation for Motherboards
- ISL6506, ISL6506B: 5VDUAL is shut down in S4/S5
sleep states
- ISL6506A: 5VDUAL stays on in S4/S5 sleep states
Pinout
ISL6506 (SOIC)
TOP VIEW
VCC 1
3V3AUX 2
S3# 3
S5# 4
GND
8 N/C
7 5VDLSB
6 DLA
5 GND
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004-2005. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.

No Preview Available !

Block Diagram
DLA
ISL6506, ISL6506A, ISL6506B
VCC
S3# S5#
www.DataSheet4U.com
5VDLSB
GND
3.5
12V POR
SENSE
SOFT START
7.5µA
MONITOR
&
CONTROL
UV DETECTOR
10µA
10µA
TEMPERATURE
MONITOR
DIGITAL
(SOFT START)
+
-
EA1
VCC
3V3AUX
Typical Application
5VSBY
12VATX 3V3ATX
5VSBY
5VATX
SLP_S3
SLP_S5
ISL6506
1 VCC
2 3V3AUX
3 S3#
4 S5#
9
1k
NC
5VDLSB
DLA
GND
8
7
6
5
Q1
Cg
(OPTIONAL)
Q2
Q3
5VDUAL
3V3DUAL
2

No Preview Available !

ISL6506, ISL6506A, ISL6506B
Absolute Maximum Ratings
Supply Voltage, V5VSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
DLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +14.5V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+ 7.0V
ESD Classification (Human Body Model) . . . . . . . . . . . . . . . . . TBD
Recommended Operating Conditions
Supply Voltage, V5VSB . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Lowest 5VSB Supply Voltage Guaranteeing Parameters . . . . +4.5V
Digital Inputs, VSx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to +5.5V
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Junction Temperature Range. . . . . . . . . . . . . . . . . . . . 0°C to 125°C
Thermal Information
www.DataSheet4U.com
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
EPSOIC Package (Notes 1, 2) . . . . . .
40
3.5
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
For Recommended soldering conditions see Tech Brief TB389.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted
PARAMETER
SYMBOL
TEST CONDITIONS
VCC SUPPLY CURRENT
Nominal Supply Current
POWER-ON RESET
I5VSB
VS3# = 5V, VS5# = 5V (S0 State)
VS3# = 0V, VS5# = 5V (S3 State)
VS5# = 0V (S5 State)
Rising 5VSB POR Threshold
Falling 5VSB POR Threshold
Rising 12V POR Threshold
3.3VAUX LINEAR REGULATOR
Regulation
3V3SB Nominal Voltage Level
3V3SB Undervoltage Threshold
3V3SB Over Current Trip
1.00kresistor between DLA and 12V Rail
V5VSBY = 5.0V, I3V3SB = 0A
V3V3SB
V3V3SB_UV
I3V3SB_TRIP ISL6506, ISL6506A, By Design
ISL6506B, By Design
5VDUAL SWITCH CONTROLLER
5VDLSB Output Drive Current
TIMING INTERVAL
I5VDLSB V5VDLSB = 4V, V5VSB = 5V
S0 to S3 Transition Delay
SOFT START
Soft Start Interval
5VDLSB Soft Start Current Source
tSS
CONTROL I/O (S3#, S5#)
High Level Input Threshold
Low Level Input Threshold
S3#, S5# Internal Pull Down Current to GND
TEMPERATURE MONITOR
Shutdown-Level Threshold
By Design
MIN TYP MAX UNITS
- 3.60 -
- 4.60 -
- 4.60 -
mA
mA
mA
- - 4.5
3.60 - 3.95
8.9 9.8 10.8
V
V
V
- - 2.0
- 3.3 -
- 2.475 -
- -1
- -2
%
V
V
A
A
20 - 35 mA
- 58 -
µs
6.55 8.2 9.85
- -7.5 -
ms
µA
- - 2.2
0.8 -
-
- 10 -
V
V
µA
- 140 -
°C
3

No Preview Available !

ISL6506, ISL6506A, ISL6506B
Functional Pin Description
VCC (Pin 1)
Provide a very well decoupled 5V bias supply for the IC to
this pin by connecting it to the ATX 5VSB output. This pin
provides all the bias for the IC as well as the input voltage for
the internal standby 3V3AUX LDO. The voltage at this pin is
monitored for power-on reset (POR) purposes.
GND (Pin 5, Pad)
Signal ground for the IC. These pins are also the ground
return for the internal 3V3AUX LDO that is active in
S3/S4/S5 sleep states. All voltage levels are measured with
respect to these pins.
S3# and S5# (Pins 3 and 4)
These pins switch the IC’s operating state from active (S0,
S1/S2) to S3 and S4/S5 sleep states. These are digital
inputs featuring internal 10µA pull down current sources on
each pin. Additional circuitry blocks illegal state transitions,
such as S4/S5 to S3. Connect S3# and S5# to the computer
system’s SLP_S3 and SLP_S5 signals, respectively.
3V3AUX (Pin 2)
Connect this pin to the 3V3DUAL output. In sleep states, the
voltage at this pin is regulated to 3.3V through an internal
pass device powered from 5VSBY through the VCC pin. In
active states, ATX 3.3V output is delivered to this node
through a fully-on NMOS transistor. During S3 and S4/S5
states, this pin is monitored for undervoltage events.
DLA (Pin 6)
This pin is an open-drain output. A 1kresistor must be
connected from this pin to the ATX 12V output. This resistor
is used to pull the gates of suitable N-MOSFETs to 12V,
which in active state, switch in the ATX 3.3V and 5V outputs
into the 3.3VAUX and 5VDUAL outputs, respectively. This pin
is also used to monitor the 12V rail during POR. If a resistor
other than 1kis used, the POR level will be affected.
5VDLSB (Pin 7)
Connect this pin to the gate of a suitable P-MOSFET.
ISL6506 and ISL6506B: In S3 sleep state, this transistor is
switched on, connecting the ATX 5VSB output to the 5VDUAL
regulator output.
ISL6506A: In S3 and S4/S5 sleep state, this transistor is
switched on, connecting the ATX 5VSB output to the 5VDUAL
regulator output.
Description
Operation
The ISL6506 controls 2 output voltages, 3.3VDUAL and
5VDUAL. It is designed for microprocessor computer
applications requiring 3.3V, 5V, 5VSB, and 12V bias input
from an ATX power supply. The IC is composed of one linear
controller/regulator supplying the cowmwpwu.tDear tsaySshteemet4sU.com
3.3VDUAL power, a dual switch controller supplying the
5VDUAL voltage, as well as all the control and monitoring
functions necessary for complete ACPI implementation.
Initialization
The ISL6506 automatically initializes upon receipt of input
power. The Power-On Reset (POR) function continually
monitors the 5VSB input supply voltage. The ISL6506 also
monitors the 12V rail to insure that the ATX rails are up
before entering into the S0 state even if both SLP_S3 and
SLP_S5 are both high.
Dual Outputs Operational Truth Table
Table 1 describes the truth combinations pertaining to the
3.3VDUAL and 5VDUAL outputs. The internal circuitry does
not allow the transition from an S4/S5 state to an S3 state.
TABLE 1. 5VDUAL OUTPUT TRUTH TABLE
S5 S3 3.3AUX
5VDL
COMMENTS
11
3.3V
5V S0/S1/S2 States (Active)
10
01
3.3V
5V
Note
S3
Maintains Previous State
00
3.3V
0V
00
3.3V
5V
NOTE: Combination Not Allowed.
S4/S5 (ISL6506 & 06B)
S4/S5 (ISL6506A)
Functional Timing Diagrams
Figures 1 (ISL6506/B) and 2 (ISL6506A) are simplified timing
diagrams, detailing the power up/down sequences of all the
outputs in response to the status of the sleep-state pins (S3#,
S5#), as well as the status of the input ATX supply. Not shown
in these diagrams is the deglitching feature used to protect
against false sleep state tripping. Additionally, the ISL6506
features a 60µs delay in transitioning from S0 to S3 states. The
transition from the S0 state to S4/S5 state is immediate.
5VSB
S3
S5
3.3V, 5V, 12V
DLA
3V3AUX
5VDLSB
5VDL
FIGURE 1. 5VDUAL AND 3.3VAUX TIMING DIAGRAM;
ISL6506 and ISL6506B
4

No Preview Available !

5VSB
S3
S5
3.3V, 5V, 12V
DLA
3V3DL
5VDLSB
5VDL
ISL6506, ISL6506A, ISL6506B
5VSB
(1V/DIV)
12VATX (2V/DIV)
5VATX (1V/DIV)
3.3VATX (1V/DIV)
www.DataSheet4U.com
3.3VDUAL
(2V/DIV)
5VDUAL
(1V/DIV)
0V
DLA
(10V/DIV)
FIGURE 2. 5VDUAL AND 3.3VAUX TIMING DIAGRAM;
ISL6506A
Soft-Start
Figures 3 and 4 show the soft-start sequence for the typical
application start-up into a sleep state. At time T0, 5VSB
(bias) is applied to the circuit. At time T1, the 5VSB
surpasses POR level. Time T2, one soft start interval after
T1, denotes the initiation of soft start. The 3.3VDUAL rail is
brought up through the internal standby LDO through an
internal digital soft start function. Figure 4 shows the 5VDUAL
rail initiating a soft start at time T2 as well. The ISL6506A will
draw 7.5µA into the 5VDLSB for a duration of one soft start
period. This current will enhance the P-MOSFET (Q2, refer
to Typical Application Schematic) in a controlled manner. At
time T3, the 3.3VDUAL is in regulation and the 5VDLSB pin
is pulled down to ground. If the 5VDUAL rail has not reached
the level of the 5VSB rail by time T3, then the rail will
experience a sudden step as the P-MOSFET gate is fully
enhanced. The soft start profile of the 5VDUAL may be
altered by placing a capacitor between the gate and drain of
the P-MOSFET. Adding this capacitor will increase the gate
capacitance and slow down the start of the 5VDUAL rail.
At time T4, the system has transitioned into S0 state and the
ATX supplies have begun to ramp up. With the ISL6506/B
(Figure 3), the 5VDUAL rail will begin to ramp up from the
5VATX rail through the body diode of the N-MOSFET (Q3).
The ISL6506A will already have the 5VDUAL rail in
regulation (Figure 4). At time T5, the 12VATX rail has
surpassed the 12V POR level. Time T6 is three soft start
cycles after the 12V POR level has been surpassed. At time
T6, three events occur simultaneously. The DLA pin is forced
to a high impedance state which allows the 12V rail to
enhance the two N-MOSFETs (Q1 and Q3) that connect the
ATX rails to the 3.3VDUAL and 5VDUAL rails. The 5VDLSB
pin is forced to a high impedance state which will turn the
P-MOSFET (Q2) off. Finally, the internal LDO which regulates
the 3.3VAUX rail in sleep states in put in standby mode.
T0 T1 T2 T3
T4 T5
TIME
T6
FIGURE 3. ISL6506 and ISL6506B SOFT-START INTERVAL
IN S4/S5 STATE AND S5 TO S0 TRANSITION
5VSB
(1V/DIV)
5VDUAL
(1V/DIV)
3.3VDUAL
(2V/DIV)
12VATX (2V/DIV)
5VATX (1V/DIV)
3.3VATX (1V/DIV)
0V
5VDLSB
(5V/DIV)
DLA
(10V/DIV)
T0 T1 T2 T3
T4 T5
TIME
T6
FIGURE 4. SOFT START INTERVAL FOR ISL6506A IN S4/S5
AND S5 TO S0 TRANSITION FOR ISL6506A AND
S3 TO S0 TRANSITION FOR ISL6506/A/B
Sleep to Wake State Transitions
Figures 3 and 4, starting at time T4, depict the transitions
from sleep states to the S0 wake state. Figure 3 shows the
transition of the ISL6506/B from the S4/S5 state to the S0
state. Figure 4 shows how the ISL6506/B will transition from
the S3 sleep state into S0 state. Figure 3 also shows how
the ISL6506A transitions from either S3 or S4/S5 in the S0
state. For all transitions, T4 depicts the system transition into
the S0 state. Here, the ATX supplies are enabled and begin
to ramp up. At time T5, the 12VATX rail has exceeded the
POR threshold for the ISL6506/B and ISL6506A. Three soft
start periods after time T5, at time T6, three events occur
5