MSC1201-XX.pdf 데이터시트 (총 20 페이지) - 파일 다운로드 MSC1201-XX 데이타시트 다운로드

No Preview Available !

E2C0017-27-Y2
¡¡SemicondSucetormiconductor
MSC1201-xx
This version:MNSoCv1.210919-7xx
Previowuswvwe.DrsaitoanS:heJeutl4.U1.9c9o6m
60-Bit VFD Tube Driver with Digital Dimming and PWM Conversion Function
GENERAL DESCRIPTION
The MSC1201-xx is a 1/2 duty vacuum fluorescent display tube driver implemented in Bi-CMOS
technology. This LSI consists of 64-bit shift registers, 64 latches, PWM conversion circuit, a digital
dimming circuit, 30-segment driver and 2-grid driver. As the MSC1201-xx has both a digital
dimming circuit and a PWM conversion circuit which converts PWM signal for lamp dimming
control to PWM signal for VFD tube dimming control, the dimming control can be realized
without any external circuit.
The interface with a MCU can be done only with 3 wires (CS, DATA and CLOCK signals). Also,
DATA and CLOCK signal lines can be shared with other peripherals because of chip select
function by CS signal.
For the general purpose code, the code number is -01. (Product name: MSC1201-01GS-2K)
For a custom code, the code number will be ordered at any time.
FEATURES
• Single supply voltage : VDD = 8 V to 18 V (built-in 5 V logic regurator)
• Operating temperature range : Ta = –40°C to +85°C
• 30-segment driver outputs (IOH = –6 mA at VOH = VDD – 0.8 V)
• 2-grid pre-driver outputs (IOH = –30 mA at VOH = VDD – 0.8 V)
• Built-in digital dimming circuit (11-bit resolution)
• Built-in oscillation circuit (external R and C, fOSC = 2.0 MHz)
• Built-in Power-On-Reset circuit.
• Lamp PWM signal Æ Buil-in PWM conversion circuit for vacuum fluorescent display tube.
• Built-in RC Oscillation (external R and C)
• Correspondence between shift register and output segment is settable optionally using built
in mask programmable 30 ¥ 30 PLA.
• Package :
44-pin plastic QFP (QFP44–P–910-0.80–2K)(Product name: MSC1201-xxGS-2K)
xx indicates the code number
1/20

No Preview Available !

¡ Semiconductor
BLOCK DIAGRAM
MSC1201-xx
www.DataSheet4U.com
VDD
GND
CS
DATA
CLOCK
SEG1
SEG30
5V
5 V Reg
&
POR Circuit
POR
30-Segment Driver
30 ¥ 30 PLA Matrix
Control
Circuit
Multiplexer
GRID1
GRID2
2-Grid Driver
OSC0
OSC1
PWMIN
VK
Latch
S1
D 64-Bit Shift Register
CK D48-59 R M3 M2 M1 M0
Mode Selector
POR
S1 S2 S3 S4
Test Mode
RC
OSC
S2
Timing Generator
R
POR
PWM Conversion Circuit
R
POR
S2
Selector
Digital Dimming Circuit
R
S3 S4
POR
DATA OUT
INH
TEST1
2/20

No Preview Available !

¡ Semiconductor
INPUT AND OUTPUT CONFIGURATION
MSC1201-xx
www.DataSheet4U.com
• Schematic Diagrams of Logic Portion Input • Schematic Diagrams of Logic Portion Input
Circuit 1
Circuit 1
VDD (5V Reg.)
VDD
(5V Reg.)
INPUT
TEST1
INH
GND GND
GND GND
• Schematic Diagrams of Logic Portion Output • Schematic Diagrams of Driver Output Circuit
Circuit
(5V Reg.)
(5V Reg.)
VDD VDD
OUTPUT
OUTPUT
GND GND
GND GND
3/20

No Preview Available !

¡ Semiconductor
PIN CONFIGURATION (TOP VIEW)
SEG22 1
SEG23 2
SEG24 3
SEG25 4
SEG26 5
SEG27 6
SEG28 7
SEG29 8
SEG30 9
GRID1 10
GRID2 11
MSC1201-xx
www.DataSheet4U.com
33 SEG10
32 SEG9
31 SEG8
30 SEG7
29 SEG6
28 SEG5
27 SEG4
26 SEG3
25 SEG2
24 SEG1
23 DATAOUT
44-Pin Plastic Package
4/20

No Preview Available !

¡ Semiconductor
PIN DESCRIPTIONS
MSC1201-xx
www.DataSheet4U.com
Pin
1-9
24-44
10, 11
16
15
18
20
19
23
22
14
21
13
12
17
Symbol I/O
SEG1-30 O Segment output pin for VFD
Description
GRID1, 2
OSC0
OSC1
CS
DATA
CLOCK
DATA
OUT
PWMIN
VK
INH
TEST1
VDD
GND
O Grid 1 and Grid 2 output pins for VFD
I RC oscillation pins. Connect a resistor between OSC1 and OSC0 pin and a capacitor
O between OSC0 and GND pin.
I Chip select input. Only when the high level is input to this pin, interfacing with a MCU
is available through "CLOCK" and "DATA" pins.
Therefore, 2-signal lines of "CLOCK" and "DATA" can be shared with other peripherals.
I Input which receives display data and digital dimming data from a MCU. Data is
shifted in at the rising edge of the shift clock.
I Serial clock input. Data that is input through "DATA" pin is input and output by
synchronization with the rising edge of the serial clock.
O Serial data output. Data is shifted out at the rising edge of the serial clock with the
delay of 64-bit time. This pin is used for cascading this LSI with other drivers such
as a LED driver.
I PWM signal input.
I Dimming select input. When the high level is input, daylight-mode output duty cycle
is about 100% for each grid time for PWM conversion and digital dimming mode.
When the low level is input, the dark-mode output duty cycle is determined by the
duty cycle of the PWM signal input to PWM IN and the digital dimming output duty
cycle is determined by digital dimming data.
I Blank Display input with a built-in pull-up resistor. When set to "L", all the drivers
output "L". When display duly is not controlled by this signal, leave this pin open.
I Test signal input pin. As this pin is used for shipping test of the LSI, leave open in the
normal operation mode.
— Power Supply
— Ground
5/20