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Philips Semiconductors
CMOS single-chip 8-bit microcontrollers
Preliminary specification
80C453/83wCw4w5.D3at/a8S7heCet44U5.c3om
DESCRIPTION
The Philips 8XC453 is an I/O expanded single-chip microcontroller
fabricated with Philips high-density CMOS technology. Philips
epitaxial substrate minimizes latch-up sensitivity.
The 8XC453 is a functional extension of the 87C51 microcontroller
with three additional I/O ports and four I/O control lines. The 8XC453
is available in 68-pin LCC packages. Four control lines associated
with port 6 facilitate high-speed asynchronous I/O functions.
The 87C453 includes an 8k × 8 EPROM, a 256 × 8 RAM, 56 I/O
lines, two 16-bit timer/counters, a seven source, two priority level,
nested interrupt structure, a serial I/O port for either a full duplex
UART, I/O expansion, or multi-processor communications, and
on-chip oscillator and clock circuits.
The 87C453 has two software selectable modes of reduced activity
for further power reduction; idle mode and power-down mode. Idle
mode freezes the CPU while allowing the RAM, timers, serial port,
and interrupt system to continue functioning. Power-down mode
freezes the oscillator, causing all other chip functions to be
inoperative while maintaining the RAM contents.
FEATURES
80C51 based architecture
Seven 8-bit I/O ports
Port 6 features:
Eight data pins
Four control pins
Direct MPU bus interface
ISA Bus Interface
Parallel printer interface
IBF and OBF interrupts
A flag latch on host write
On the microcontroller:
8k × 8 EPROM
Quick pulse programming algorithm
Two-level program security system
256 × 8 RAM
Two 16-bit counter/timers
Two external interrupts
External memory addressing capability
64k ROM and 64k RAM
Low power consumption:
Normal operation: less than 24mA at 5V, 16MHz
Idle mode
Power-down mode
Reduced EMI
Full-duplex enhanced UART
Framing error detection
Automatic address recognition
LCC PIN FUNCTIONS
9
1
10
61
60
LCC
26 44
Pin Function
1 EA/VPP
2 P2.0/A8
3 P2.1/A9
4 P2.2/A10
5 P2.3/A11
6 P2.4/A12
7 P2.5/A13
8 P2.6/A14
9 P2.7/A15
10 P0.7/AD7
11 P0.6/AD6
12 P0.5/AD5
13 P0.4/AD4
14 P0.3/AD3
15 P0.2/AD2
16 P0.1/AD1
17 P0.0/AD0
18 VCC
19 P4.7
20 P4.6
21 P4.5
22 P4.4
23 P4.3
27 43
Pin Function
24 P4.2
25 P4.1
26 P4.0
27 P1.0
28 P1.1
29 P1.2
30 P1.3
31 P1.4
32 P1.5
33 P1.6
34 P1.7
35 RST
36 P3.0/RxD
37 P3.1/TxD
38 P3.2/INTO
39 P3.3/INT1
40 P3.4/T0
41 P3.5/T1
42 P3.6/WR
43 P3.7/RD
44 P5.0
45 P5.1
46 P5.2
Pin Function
47 P5.3
48 P5.4
49 P5.5
50 P5.6
51 P5.7
52 XTAL2
53 XTAL1
54 VSS
55 ODS
56 IDS
57 BFLAG
58 AFLAG
59 P6.0
60 P6.1
61 P6.2
62 P6.3
63 P6.4
64 P6.5
65 P6.6
66 P6.7
67 PSEN
68 ALE/PROG
SU00157
1996 Aug 15
3-311

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Philips Semiconductors
CMOS single-chip 8-bit microcontrollers
Preliminary specification
80C453/83wCw4w5.D3at/a8S7heCet44U5.c3om
ORDERING INFORMATION
EPROM1
ROMLESS
ROM
P87C453EBAA OTP P80C453EBAA P83C453EBAA
P87C453EFAA OTP P80C453EFAA P83C453EFAA
P87C453EBLKA UV
P87C453EFLKA UV
NOTE:
1. OTP = One-Time Programmable EPROM.
UV = Erasable EPROM.
TEMPERATURE °C AND PACKAGE
68–Pin Plastic Leaded Chip Carrier, 0 to +70
68–Pin Plastic Leaded Chip Carrier, –40 to +85
68-Pin Ceramic Leaded Chip Carrier with window,
0 to +70
68-Pin Ceramic Leaded Chip Carrier with window,
–40 to +85
FREQ.
(MHz)
PKG.
DWG #
3.5 to 16 SOT188-3
3.5 to 16 SOT188-3
3.5 to 16 1473A
3.5 to 16 1473A
LOGIC SYMBOL
VCC VSS
XTAL1
XTAL2
RST
EA/VPP
PSEN
ALE/PROG
RxD
TxD
INT0
INT1
T0
T1
WR
RD
ADDRESS AND
DATA BUS
ADDRESS BUS
PORT 6 CONTROL
ODS
IDS
BFLAG
AFLAG
SU00085
1996 Aug 15
3-312

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Philips Semiconductors
CMOS single-chip 8-bit microcontrollers
Preliminary specification
80C453/83wCw4w5.D3at/a8S7heCet44U5.c3om
BLOCK DIAGRAM
P0.0–P0.7
P2.0–P2.7
P4.0–P4.7
P5.0–5.7
VCC
VSS
RAM ADDR
REGISTER
PORT 0
DRIVERS
PORT 2
DRIVERS
PORT 4
DRIVERS
PORT 5
DRIVERS
256 BYTES
RAM
PORT 0
LATCH
PORT 2
LATCH
PORT 4
LATCH
PORT 5
LATCH
8K x 8
EPROM
B
REGISTER
ACC
TMP2
TMP1
STACK
POINTER
ALU
PSW
PCON
PSW
TL1
CSR
SCON TMOD
TH0 TL0
DPH DPL
SBUF IE
TCON
TH1
AUXR
IP
INTERRUPT, SERIAL
PORT AND TIMER BLOCKS
PSEN
ALE/PROG
EAVPP
RST
TIMING
AND
CONTROL
PD
OSCILLATOR
XTAL1
XTAL2
PORT 1
LATCH
PORT 1
DRIVERS
P1.0–P1.7
PORT 6
LATCH
PORT 6
DRIVERS
P6.0–P6.7
PORT 3
LATCH
PORT 6
CONTROL/STATUS
PORT 3
DRIVERS
IDS ODS BFLAG
AFLAG
P3.0–P3.7
PROGRAM
ADDRESS
REGISTER
BUFFER
PC
INCRE-
MENTER
PROGRAM
COUNTER
DPTR
SU00158
1996 Aug 15
3-313

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Philips Semiconductors
CMOS single-chip 8-bit microcontrollers
Preliminary specification
80C453/83wCw4w5.D3at/a8S7heCet44U5.c3om
PIN DESCRIPTION
MNEMONIC
VSS
VCC
P0.0–0.7
PIN NO.
54
18
17-10
P1.0–P1.7
27-34
P2.0–P2.7
2-9
P3.0–P3.7
36-43
P4.0–P4.3
P4.0–P4.7
P5.0–P5.7
P6.0–P6.7
36
37
38
39
40
41
42
43
26-19
44-51
59-66
ODS
IDS
BFLAG
AFLAG
RST
ALE/PROG
55
56
57
58
35
68
PSEN
67
EA/VPP
XTAL1
XTAL2
1
53
52
TYPE NAME AND FUNCTION
I Ground: 0V reference.
I Power Supply: This is the power supply voltage for normal, idle, and power-down operation.
I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 is also the multiplexed data and low-order
address bus during accesses to external memory. External pull-ups are required during program
verification. Port 0 can sink/source eight LS TTL inputs.
I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 receives the low-order address
bytes during program memory verification. Port 1 can sink/source three LS TTL inputs, and drive CMOS
inputs without external pull-ups.
I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 emits the high-order address
bytes during access to external memory and receives the high-order address bits and control signals
during program verification. Port 2 can sink/source three LS TTL inputs, and drive CMOS inputs without
external pull-ups.
I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 can sink/source three LS TTL
inputs, and drive CMOS inputs without external pull-ups. Port 3 also serves the special functions listed
below:
I RxD (P3.0): Serial input port
O TxD (P3.1): Serial output port
I INT0 (P3.2): External interrupt
I INT1 (P3.3): External interrupt
I T0 (P3.4): Timer 0 external input
I T1 (P3.5): Timer 1 external input
O WR (P3.6): External data memory write strobe
O RD (P3.7): External data memory read strobe
I/O Port 4: Port 4 is an 8-bit bidirectional I/O port with internal pull-ups. Port 4 can sink/source three LS TTL
I/O inputs and drive CMOS inputs without external pull-ups.
I/O Port 5: Port 5 is an 8-bit bidirectional I/O port with internal pull-ups. Port 5 can sink/source three LS TTL
inputs and drive CMOS inputs without external pull-ups.
I/O Port 6: Port 6 is a specialized 8-bit bidirectional I/O port with internal pull-ups. This special port can
sink/source three LS TTL inputs and drive CMOS inputs without external pull-ups. Port 6 can be used in a
strobed or non-strobed mode of operation. Port 6 works in conjunction with four control pins that serve the
functions listed below:
I ODS: Output data strobe
I IDS: Input data strobe
I/O BFLAG: Bidirectional I/O pin with internal pull-ups
I/O AFLAG: Bidirectional I/O pin with internal pull-ups
I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An
internal pull-down resistor permits a power-on reset using only an external capacitor connected to VCC.
I/O Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an
access to external memory. ALE is activated at a constant rate of 1/6 the oscillator frequency except during
an external data memory access, at which time one ALE is skipped. ALE can sink/source three LS TTL
inputs and drive CMOS inputs without external pull-ups. This pin is also the program pulse during EPROM
programming.
O Program Store Enable: The read strobe to external program memory. PSEN is activated twice each
machine cycle during fetches from external program memory. However, when executing out of external
program memory, two activations of PSEN are skipped during each access to external program memory.
PSEN is not activated during fetches from internal program memory. PSEN can sink/source eight LS TTL
inputs and drive CMOS inputs without an external pull-up. This pin should be tied low during programming.
I Instruction Execution Control/Programming Supply Voltage: When EA is held high, the CPU executes
out of internal program memory, unless the program counter exceeds 1FFFH. When EA is held low, the
CPU executes out of external program memory. EA must never be allowed to float. This pin also receives
the 12.75V programming supply voltage (VPP) during EPROM programming.
I Crystal 1: Input to the inverting oscillator amplifier that forms the oscillator. This input receives the external
oscillator when an external oscillator is used.
O Crystal 2: An output of the inverting amplifier that forms the oscillator. This pin should be floated when an
external oscillator is used.
1996 Aug 15
3-314

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Philips Semiconductors
CMOS single-chip 8-bit microcontrollers
Preliminary specification
80C453/83wCw4w5.D3at/a8S7heCet44U5.c3om
Table 1.
SYMBOL
ACC*
B*
CSR*#
DPTR
DPH
DPL
IP*
87C453 Special Function Registers
DESCRIPTION
DIRECT
ADDRESS MSB
Accumulator
E0H E7
B register
F0H F7
EF
Port 6 command/status
E8H
MB1
Data pointer (2 bytes)
Data pointer high
83H
Data pointer low
82H
BF
Interrupt priority
B8H –
BIT NAMES AND ADDRESSES
E6
F6
EE
MB0
E5
F5
ED
MA1
E4
F4
EC
MA0
E3
F3
EB
OBFC
E2
F2
EA
IDSM
BE BD BC BB BA
POB PIB PS PT1 PX1
LSB
E1 E0
F1 F0
E9 E8
OBF IBF
B9 B8
PT0 PX0
RESET
VALUE
00H
00H
FCH
00H
00H
x0000000B
AUXR# Auxiliary register
IE*
P0*
P1*
P2*
P3*
P4*#
P5*#
P6*#
PCON
Interrupt enable
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Power control
8EH
A8H
80H
90H
A0H
B0H
C0H
C8H
D8H
87H
– – – – – – AF AO x0000000B
AF AE AD AC AB AA A9 A8
EA IOB IIB ES ET1 EX1 ET0 EX0 00000000B
87 B6 85 84 83 82 81 80 FFH
97 96 95 94 93 92 91 90 FFH
A7 A6 A5 A4 A3 A2 A1 A0 FFH
B7 B6 B5 B4 B3 B2 B1 B0 FFH
C7 C6 C5 C4 C3 C2 C1 C0 FFH
CF CE CD CC CB CA C9 C8 FFH
DF DE DD DC DB DA D9 D8 FFH
SMOD1 SMOD0 –
POF1 GF1 GF0 PD
IDL 00xx0000B
PSW*
SADDR#
SADEN#
SBUF
Program status word
Slave Address
Slave Address Mask
Serial data buffer
SCON*
SP
Serial port control
Stack pointer
TCON* Timer/counter control
D0H
A9H
B9H
99H
98H
81H
88H
D7
CY
9F
SM0
8F
TF1
D6 D5 D4 D3 D2 D1
AC F0 RS1 RS0 OV –
9E 9D 9C 9B 9A
SM1 SM2 REN TB8 RB8
99
TI
8E 8D 8C 8B 8A 89
TR1 TF0 TR0 IE1 IT1 IE0
D0
P 00H
00H
00H
xxxxxxxxB
98
RI 00H
07H
88
IT0 00H
TMOD Timer/counter mode
89H GATE C/T M1 M0 GATE C/T M1 M0 00H
TH0 Timer 0 high byte
8CH
00H
TH1 Timer 1 high byte
8DH
00H
TL0 Timer 0 low byte
8AH
00H
TL1 Timer 1 low byte
8BH
NOTES:
* SFRs are bit addressable.
# SFRs are modified from or added to the 80C51 SFRs.
1. REset value depends on reset source.
00H
1996 Aug 15
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