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19-3486; Rev 1; 11/05
10Gbps Clock and Data Recovery
with Limiting Amplifier
General Description
The MAX3991 is a 10Gbps clock and data recovery
(CDR) with limiting amplifier IC for XFP optical receivers.
The MAX3991 and the MAX3992 (CDR with equalizer)
form a signal conditioner chipset for use in XFP trans-
ceiver modules. The chipset is XFI compliant and offers
multirate operation for data rates from 9.95Gbps to
11.1Gbps.
The MAX3991 has 7mVP-P input sensitivity (BER 10-12),
which allows direct connection to a transimpedance
amplifier without the use of a stand-alone limiting amplifi-
er. The phase-locked loop (PLL) is optimized for jitter tol-
erance and provides 0.6UI of high-frequency tolerance
in SONET, Ethernet, and Fibre-Channel applications. The
MAX3991 output provides 27% margin to the XFP eye
mask specification.
An AC-based power detector toggles the loss-of-signal
(LOS) output when the input signal swing is below the
user-programmed assert threshold. An external refer-
ence clock, with frequency equal to 1/64 or 1/16 of the
serial data rate is used to aid in frequency acquisition. A
loss-of-lock (LOL) indicator is provided to indicate the
lock status of the receiver PLL.
The MAX3991 is available in a 4mm x 4mm, 24-pin QFN
package. It consumes 350mW from a single +3.3V supply
and operates over the 0°C to +85°C temperature range.
Features
Multirate Operation from 9.95Gbps to 11.1Gbps
7mVP-P Input Sensitivity (BER 10-12)
0.6UIP-P Total High-Frequency Jitter Tolerance
Low-Output Jitter Generation: 7mUIRMS
Low-Output Deterministic Jitter: 4.6psP-P
XFI-Compliant Output Interface
LOS Indicator with Programmable Threshold
LOL Indicator
Power Dissipation: 350mW
Ordering Information
PART
TEMP RANGE PIN-
PACKAGE
MAX3991UTG
0°C to +85°C 24 QFN
MAX3991UTG+* 0°C to +85°C 24 QFN
*Future product—contact factory for availability.
+Denotes lead-free package.
PKG
CODE
T2444-4
T2444-4
Applications
9.95Gbps to 11.1Gbps Optical XFP Modules
SONET OC-192/SDH STM-64 XFP Transceivers
10.3Gbps/11.1Gbps Ethernet XFP Transceivers
10.5Gbps Fibre-Channel XFP Transceivers
10Gbps DWDM Transceivers
Typical Application Circuit appears at end of data sheet.
TOP VIEW
Pin Configuration
24 23 22 21 20 19
VCC 1
18 VCC
GND 2
17 GND
SDI+ 3
SDI- 4
MAX3991
16 SDO+
15 SDO-
GND 5
14 GND
VCC 6
13 VCC
7 8 9 10 11 12
4mm x 4mm QFN*
*THE EXPOSED PAD MUST BE CONNECTED TO CIRCUIT-BOARD GROUND FOR
PROPER THERMAL AND ELECTRICAL PERFORMANCE.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

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10Gbps Clock and Data Recovery
with Limiting Amplifier
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC..............................................-0.5V to +4.0V
Input Voltage Levels
(SDI+, SDI-, REFCLK+,
REFCLK-) ....................................(VCC - 1.0V) to (VCC + 0.5V)
CML Output Voltage
(SDO+, SDO-, SCLKO+,
SLCKO-) ......................................(VCC - 1.0V) to (VCC + 0.5V)
Voltage at (CFIL, LOL, VTH, POL,
LOS, FCTL1, FCTL2) ..............................-0.5V to (VCC + 0.5V)
Continuous Power Dissipation (TA = +85°C)
24-Pin QFN (derate 20.8mW/°C above +85°C) .........1355mW
Junction Temperature Range ............................-40°C to +150°C
Storage Temperature Range.............…………..-55°C to +150°C
Lead Temperature (soldering, 10s) ..……………………..+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(See Table 1 for operating conditions. Typical values at VCC = +3.3V, TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
Supply Current
ICC
DATA INPUT SPECIFICATION (SDI±)
Single-Ended Input Resistance
Differential Input Resistance
RSE
RD
Single-Ended Input Resistance
Matching
CONDITIONS
MIN TYP
106
42 50
84 100
Differential Input Return Loss
SDD11
0.1GHz to 5.5GHz (Note 1)
5.5GHz to 12GHz (Note 1)
12.5
6
DC Cancellation Loop Low-
Frequency Cutoff
30
REFERENCE CLOCK SPECIFICATION (REFCLK±)
Single-Ended Input Resisitance
Differential Input Resistance
CML OUTPUT SPECIFICATION (SDO±)
SDO± Differential Output Swing
(Note 2)
84 100
168 200
575 650
SDO± Output Common-Mode
Voltage
SCLKO± Differential Output
Single-Ended Output Resistance
Differential Output Resistance
Single-Ended Output Resistance
Matching
RL = 50to VCC
RO
VCC -
0.16
380
42 50
84 100
Differential Output Return Loss
Common-Mode Output Return
Rise/Fall Time
Output AC Common Mode
Power-Down Assert Time
SDD22
SCC22
0.1GHz to 5.5GHz (Note 1)
5.5GHz to 12GHz (Note 1)
0.1GHz to 15GHz (Note 1)
(20% to 80%) (Note 2)
(Note 2)
(Note 3)
13
8
5
18 23
MAX
140
UNITS
mA
58
116
±5 %
dB
kHz
116
232
725 mVP-P
V
mVP-P
58
116
±5 %
dB
dB
30 ps
10 mVRMS
50 µs
2 _______________________________________________________________________________________

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10Gbps Clock and Data Recovery
with Limiting Amplifier
ELECTRICAL CHARACTERISTICS (continued)
(See Table 1 for operating conditions. Typical values at VCC = +3.3V, TA = +25°C, unless otherwise noted.)
PARAMETER
JITTER SPECIFICATION
Jitter Peaking
Jitter Transfer Bandwidth
Sinusoidal Jitter Tolerance
Jitter Generation
SYMBOL
CONDITIONS
120kHz < f 8MHz (Notes 2, 4)
JP f 120kHz (Note 5)
JBW (Notes 2, 4)
f = 400kHz
(Notes 2, 4, 7)
f = 4MHz
f = 80MHz
(Notes 2, 4, 8)
MIN TYP MAX
3.0
0.55
0.45
0.05 0.25
0.03
5.6 8.0
>3 (Note 6)
>0.6 (Note 6)
>0.5 (Note 6)
4.5 11.0
Serial Data Output Deterministic
Jitter
DJ PRBS 27 - 1 (Note 2)
4.6 13
PLL ACQUISITION/LOCK SPECIFICATION
Acquisition Time
Figures 1, 2 (Note 2)
200
LOL Assert Time
Maximum Frequency Pullin Time
Figure 1 (Note 2)
(Note 9)
90
2
Frequency Difference at which
LOL is Asserted
f/fREFCLK
f = |fVCO / N - fREFCLK|,
N = 16 or 64
651
Frequency Difference at which
LOL is DeAsserted
f/fREFCLK
f = |fVCO / N - fREFCLK|,
N = 16 or 64
500
LOSS-OF-SIGNAL (LOS) SPECIFICATION
UNITS
dB
MHz
UIP-P
mUIRMS
psP-P
µs
µs
ms
ppm
ppm
VTH Control Voltage Range
VTH
150 500 mV
LOS Gain Factor
VTH/
VLOS_ASSERT
Minimum LOS Assert Voltage
VLOS_ASSERT
Maximum LOS Assert Voltage
LOS Gain-Factor Accuracy
VLOS_ASSERT
(Notes 2, 10)
LOS Hysteresis
(Notes 2, 11)
LOS Gain-Factor Stability
(Note 2) Overtemperature and supply
LOS Assert Time
Figure 2 (Note 2)
LOS Deassert Time
Figure 2 (Note 2)
VTH Input Current
LVTTL INPUT/OUTPUT SPECIFICATION (LOL, LOS, FCTL1, FCTL2)
Input High Voltage
Input Low Voltage
Input Current
VIH
VIL
Output High Voltage
VOH
Sourcing 30µA
Output Low Voltage
VOL Sinking 1mA
10
15
50
-1.5 +1.5
3.5 3.7 3.9
-10 +10
3 90
90
-5 +5
2.0
-30
VCC -
0.5
0.8
+30
0.4
V/V
mV
mV
dB
dB
%
µs
µs
µA
V
V
µA
V
V
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10Gbps Clock and Data Recovery
with Limiting Amplifier
ELECTRICAL CHARACTERISTICS (continued)
(See Table 1 for operating conditions. Typical values at VCC = +3.3V, TA = +25°C, unless otherwise noted.)
Note 1: Measured with 100mVP-P differential amplitude.
Note 2: Guaranteed by design and characterization.
Note 3: Measured from the time that the FCTL1 input goes high with FCTL2 = 0 to the time when the supply current drops to less
than 40% of the nominal value.
Note 4: Measured with PRBS = 231 - 1.
Note 5: Larger CFILT can be used to reduce jitter peaking at 120kHz. A larger CFILT will increase acquisition time. CFILT should
not exceed 200nF.
Note 6: Measurement limited by test equipment.
Note 7: Jitter tolerance is for BER 10-12, measured with additional 0.1UI deterministic jitter and 40mVP-P differential input.
Note 8: Measured with 50kHz to 80MHz SONET filter.
Note 9: Applies on power-up, after standby.
Note 10: Over process, temperature, and supply.
Note 11: Hysteresis is defined as 20Log(VLOS-DEASSERT / VLOS-ASSERT).
Table 1. Operating Conditions (Unless otherwise noted, FCTL1 = FCTL2 = 0.)
PARAMETER
SYMBOL
CONDITIONS
Supply Voltage
Ambient Temperature
Input Data Rate
VCC
TA
Rb
SDI± Differential Input Voltage Swing
VD
Load Resistance
RL RL is AC-coupled
REFCLK± Differential Input Voltage
Swing
REFCLK Duty Cycle
REFCLK Frequency
fREFCLK
REFCLK Accuracy
REFCLK Rise/Fall Times (20% to
80%)
REFCLK Random Jitter
Relative to Rb / 16 or Rb / 64
fREFCLK= Rb / 64
fREFCLK= Rb / 16
Noise bandwidth < 100MHz
MIN TYP MAX
3.0 3.6
0 +85
(See Table 2 )
15 1000
50
300 1600
30
-100
Rb / 16
Rb / 64
70
+100
1200
300
10
UNITS
V
°C
Gbps
mVP-P
mVP-P
%
GHz
ppm
ps
psRMS
Table 2. Serial Data Rate and Reference Clock Frequency
APPLICATION
DATA RATE (Rb)
(Gbps)
/16 REFERENCE CLOCK
FREQUENCY (MHz)
OC-192 SONET – SDH64
OC-192 SONET Over FEC
ITU G.709
10Gbps Ethernet, IEEE 802.3ae
10 Gigabit Ethernet Over ITU G.709
10Gbps Fibre Channel
9.95328
10.664
10.709
10.3125
11.09573
10.51875
622.08
666.5
669.3125
644.53125
693.483125
657.421875
Note: The part should be in standby mode when data rates are being switched.
/64 REFERENCE CLOCK
FREQUENCY (MHz)
155.52
166.625
167.328125
161.1328125
173.3707813
164.355469
4 _______________________________________________________________________________________

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10Gbps Clock and Data Recovery
with Limiting Amplifier
f/fREFCLK
651ppm
500ppm
LOL
ASSERT TIME
LOL
*ASSERT AND ACQUISITION TIME ARE DEFINED
WITH A VALID REFERENCE CLOCK APPLIED.
Figure 1. RX LOL Assert and PLL Acquisition Time
ACQUISITION
TIME
DATA INPUT
POWER
LOS ASSERT TIME
LOS DEASSERT TIME
LOS
LOL
Figure 2. LOS Assert/Deassert Time
ACQUISITION TIME
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